Intel A2Y15AV Ficha Técnica descarregar pdf (Página 97)

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Datasheet, Volume 2 97

Processor Configuration Registers

2.6.15 MBASE—Memory Base Address Register

This register controls the processor to PCI Express-G non-prefetchable memory access

routing based on the following formula:

MEMORY_BASE ≤ address ≤ MEMORY_LIMIT

The upper 12 bits of the register are read/write and correspond to the upper 12

address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-

only and return zeroes when read. This register must be initialized by the configuration

software. For the purpose of address decode, address bits A[19:0] are assumed to be

0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB

boundary.

B/D/F/Type: 0/1/0–2/PCI

Address Offset: 20–21h

Reset Value: FFF0h

Access: RW

Size: 16 bits

BIOS Optimal Default 0h

Bit Access

Reset

Value

RST/

PWR

Description

15:4 RW FFFh Uncore

Memory Address Base (MBASE)

This field corresponds to A[31:20] of the lower limit of the

memory range that will be passed to PCI Express-G.

3:0 RO 0h Reserved (RSVD)

1 2 ... 92 93 94 95 96 97 98 99 100 101 102 ... 341 342

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