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Document Number: 326769-002Mobile 3rd Generation Intel® Core™ Processor FamilyDatasheet – Volume 2 of 2June 2012

10 Datasheet, Volume 2Figures2-1 System Address Range Example ...192-2 DOS Lega

Processor Configuration Registers100 Datasheet, Volume 22.6.18 PMLIMIT—Prefetchable Memory Limit Address RegisterThis register, in conjunction with th

Datasheet, Volume 2 101Processor Configuration Registers 2.6.20 PMLIMITU—Prefetchable Memory Limit Address Upper RegisterThe functionality associated

Processor Configuration Registers102 Datasheet, Volume 22.6.22 INTRLINE—Interrupt Line RegisterThis register contains interrupt line routing informati

Datasheet, Volume 2 103Processor Configuration Registers 2.6.24 BCTRL—Bridge Control RegisterThis register provides extensions to the PCICMD register

Processor Configuration Registers104 Datasheet, Volume 22.6.25 PM_CAPID—Power Management Capabilities Register2RW 0bUncoreISA Enable (ISAEN)Needed to

Datasheet, Volume 2 105Processor Configuration Registers 2.6.26 PM_CS—Power Management Control/Status Register24:22 RO 000b UncoreAuxiliary Current (A

Processor Configuration Registers106 Datasheet, Volume 28RW 0bUncorePME Enable (PMEE) This bit indicates that this device does not generate PME# asser

Datasheet, Volume 2 107Processor Configuration Registers 2.6.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities RegisterThis capability is used to un

Processor Configuration Registers108 Datasheet, Volume 22.6.29 MSI_CAPID—Message Signaled Interrupts Capability ID RegisterWhen a device supports MSI

Datasheet, Volume 2 109Processor Configuration Registers 2.6.30 MC—Message Control RegisterSystem software can modify bits in this register, but the d

Datasheet, Volume 2 11Revision History§ §Revision NumberDescriptionRevision Date001 Initial release April 2012002• Updated Section 2.6 to reflect supp

Processor Configuration Registers110 Datasheet, Volume 22.6.31 MA—Message Address Register2.6.32 MD—Message Data Register2.6.33 PEG_CAPL—PCI Express-G

Datasheet, Volume 2 111Processor Configuration Registers 2.6.34 PEG_CAP—PCI Express-G Capabilities RegisterThis register indicates PCI Express* device

Processor Configuration Registers112 Datasheet, Volume 22.6.36 DCTL—Device Control RegisterThis register provides control for PCI Express* device spec

Datasheet, Volume 2 113Processor Configuration Registers 2.6.37 DSTS—Device Status RegisterThis register reflects status corresponding to controls in

Processor Configuration Registers114 Datasheet, Volume 22.6.38 LCAP—Link Capabilities RegisterB/D/F/Type: 0/1/0–2/PCIAddress Offset: AC–AFhReset Value

Datasheet, Volume 2 115Processor Configuration Registers 18 RO 0b UncoreClock Power Management (CPM) A value of 1b in this bit indicates that the comp

Processor Configuration Registers116 Datasheet, Volume 22.6.39 LCTL—Link Control RegisterThis register allows control of PCI Express* link.B/D/F/Type:

Datasheet, Volume 2 117Processor Configuration Registers 6RW 0bUncoreCommon Clock Configuration (CCC) 0 = Indicates that this component and the compon

Processor Configuration Registers118 Datasheet, Volume 22.6.40 LSTS—Link Status RegisterThe register indicates PCI Express* link status.B/D/F/Type: 0/

Datasheet, Volume 2 119Processor Configuration Registers 2.6.41 SLOTCAP—Slot Capabilities RegisterNote: PCI Express* Hot-Plug is not supported on the

12 Datasheet, Volume 2

Processor Configuration Registers120 Datasheet, Volume 216:15 RW-O 00b UncoreSlot Power Limit Scale (SPLS) This field specifies the scale used for the

Datasheet, Volume 2 121Processor Configuration Registers 2.6.42 SLOTCTL—Slot Control RegisterNote: PCI Express* Hot-Plug is not supported on the proce

Processor Configuration Registers122 Datasheet, Volume 27:6 RO 00b UncoreReserved for Attention Indicator Control (AIC) If an Attention Indicator is i

Datasheet, Volume 2 123Processor Configuration Registers 2.6.43 SLOTSTS—Slot Status RegisterThis is a PCI Express* Slot related register.B/D/F/Type: 0

Processor Configuration Registers124 Datasheet, Volume 23RW1C 0b UncorePresence Detect Changed (PDC) A pulse indication that the inband presence detec

Datasheet, Volume 2 125Processor Configuration Registers 2.6.44 RCTL—Root Control RegisterThis register allows control of PCI Express* Root Complex sp

Processor Configuration Registers126 Datasheet, Volume 22.6.45 RSTS—Root Status RegisterThis register provides information about PCI Express* Root Com

Datasheet, Volume 2 127Processor Configuration Registers 2.6.46 DCAP2—Device Capabilities 2 RegisterB/D/F/Type: 0/1/0–2/PCIAddress Offset: C4–C7hReset

Processor Configuration Registers128 Datasheet, Volume 22.6.47 DCTL2—Device Control 2 RegisterB/D/F/Type: 0/1/0–2/PCIAddress Offset: C8–C9hReset Value

Datasheet, Volume 2 129Processor Configuration Registers 2.6.48 LCAP2—Link Capabilities 2 Register2.6.49 LCTL2—Link Control 2 RegisterB/D/F/Type: 0/1/

Datasheet, Volume 2 13Introduction 1 IntroductionThis is Volume 2 of the Datasheet for the following products: • Mobile 3rd Generation Intel® Core™ pr

Processor Configuration Registers130 Datasheet, Volume 26RWS 0bPowergoodSelectable De-emphasis (selectabledeemphasis) When the Link is operating at 5

Datasheet, Volume 2 131Processor Configuration Registers 2.6.50 LSTS2—Link Status 2 RegisterB/D/F/Type: 0/1/0–2/PCIAddress Offset: D2–D3hReset Value:

Processor Configuration Registers132 Datasheet, Volume 22.7 PCI Device 1 Function 0–2 Extended Configuration RegistersTable 2-10. PCI Device 1 Functio

Datasheet, Volume 2 133Processor Configuration Registers 2.7.1 PVCCAP1—Port VC Capability Register 1This register describes the configuration of PCI E

Processor Configuration Registers134 Datasheet, Volume 22.7.3 PVCCTL—Port VC Control RegisterB/D/F/Type: 0/1/0–2/MMRAddress Offset: 10C–10DhReset Valu

Datasheet, Volume 2 135Processor Configuration Registers 2.7.4 VC0RCAP—VC0 Resource Capability RegisterB/D/F/Type: 0/1/0–2/MMRAddress Offset: 110–113h

Processor Configuration Registers136 Datasheet, Volume 22.7.5 VC0RCTL—VC0 Resource Control RegisterThis register controls the resources associated wit

Datasheet, Volume 2 137Processor Configuration Registers 2.7.6 VC0RSTS—VC0 Resource Status RegisterThis register reports the Virtual Channel specific

Processor Configuration Registers138 Datasheet, Volume 22.7.8 EQCTL0_1—Lane 0/1 Equalization Control RegisterLane Equalization Control Register (2 lan

Datasheet, Volume 2 139Processor Configuration Registers 2.7.9 EQCTL2_3—Lane 2/3 Equalization Control RegisterLane Equalization Control Register (2 la

Introduction14 Datasheet, Volume 2

Processor Configuration Registers140 Datasheet, Volume 22.7.10 EQCTL4_5—Lane 4/5 Equalization Control RegisterLane Equalization Control Register (2 la

Datasheet, Volume 2 141Processor Configuration Registers 2.7.11 EQCTL6_7—Lane 6/7 Equalization Control RegisterLane Equalization Control Register (2 l

Processor Configuration Registers142 Datasheet, Volume 22.7.12 EQCTL8_9—Lane 8/9 Equalization Control RegisterLane Equalization Control Register (2 la

Datasheet, Volume 2 143Processor Configuration Registers 2.7.13 EQCTL10_11—Lane 10/11 Equalization Control RegisterLane Equalization Control Register

Processor Configuration Registers144 Datasheet, Volume 22.7.14 EQCTL12_13—Lane 12/13 Equalization Control RegisterLane Equalization Control Register (

Datasheet, Volume 2 145Processor Configuration Registers 2.7.15 EQCTL14_15—Lane 14/15 Equalization Control RegisterLane Equalization Control Register

Processor Configuration Registers146 Datasheet, Volume 22.7.16 EQCFG—Equalization Configuration RegisterLane Equalization Control Register (2 lanes ar

Datasheet, Volume 2 147Processor Configuration Registers 5:2 RW 0h UncoreBypass Coefficients During Phase 3 (BYPCOEFPH3) Bit [0]: Controls the value

Processor Configuration Registers148 Datasheet, Volume 22.8 PCI Device 2 Configuration Space RegistersTable 2-11. PCI Device 2 Configuration Space Reg

Datasheet, Volume 2 149Processor Configuration Registers 2.8.1 VID2—Vendor Identification RegisterThis register combined with the Device Identificatio

Datasheet, Volume 2 15Processor Configuration Registers 2 Processor Configuration RegistersThis chapter contains the following:• Register terminology•

Processor Configuration Registers150 Datasheet, Volume 22.8.3 PCICMD2—PCI Command RegisterThis 16-bit register provides basic control over the IGD&apo

Datasheet, Volume 2 151Processor Configuration Registers 2.8.4 PCISTS2—PCI Status RegisterPCISTS is a 16-bit status register that reports the occurren

Processor Configuration Registers152 Datasheet, Volume 22.8.5 RID2—Revision Identification RegisterThis register contains the revision number for Devi

Datasheet, Volume 2 153Processor Configuration Registers 2.8.7 CLS—Cache Line Size RegisterThe IGD does not support this register as a PCI slave.2.8.8

Processor Configuration Registers154 Datasheet, Volume 22.8.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address RegisterThis register

Datasheet, Volume 2 155Processor Configuration Registers 2.8.11 GMADR—Graphics Memory Range Address RegisterGMADR is the PCI aperture used by S/W to a

Processor Configuration Registers156 Datasheet, Volume 22.8.12 IOBAR—I/O Base Address RegisterThis register provides the Base offset of the I/O regist

Datasheet, Volume 2 157Processor Configuration Registers 2.8.14 SID2—Subsystem Identification RegisterThis register is used to uniquely identify the s

Processor Configuration Registers158 Datasheet, Volume 22.8.17 INTRLINE—Interrupt Line RegisterThis 8-bit register is used to communicate interrupt li

Datasheet, Volume 2 159Processor Configuration Registers 2.8.20 MAXLAT—Maximum Latency RegisterThe Integrated Graphics Device has no requirement for t

Processor Configuration Registers16 Datasheet, Volume 22.2 PCI Devices and FunctionsNote: Not all devices are enabled in all configurations.Table 2-2.

Processor Configuration Registers160 Datasheet, Volume 22.9 Device 2 IO Registers2.9.1 Index—MMIO Address RegisterMMIO_INDEX: A 32 bit I/O write to th

Datasheet, Volume 2 161Processor Configuration Registers 2.10 PCI Device 6 RegistersTable 2-13. PCI Device 6 Register Address Map (Sheet 1 of 2)Addres

Processor Configuration Registers162 Datasheet, Volume 22.10.1 VID—Vendor Identification RegisterThis register combined with the Device Identification

Datasheet, Volume 2 163Processor Configuration Registers 2.10.2 DID—Device Identification RegisterThis register combined with the Vendor Identificatio

Processor Configuration Registers164 Datasheet, Volume 28RW 0bUncoreSERR# Message Enable (SERRE)This bit controls the root port’s SERR# messaging. The

Datasheet, Volume 2 165Processor Configuration Registers 2RW 0bUncoreBus Master Enable (BME)THis bit controls the ability of the PEG port to forward M

Processor Configuration Registers166 Datasheet, Volume 22.10.4 PCISTS—PCI Status RegisterThis register reports the occurrence of error conditions asso

Datasheet, Volume 2 167Processor Configuration Registers 2.10.5 RID—Revision Identification RegisterThis register contains the revision number of the

Processor Configuration Registers168 Datasheet, Volume 22.10.6 CC—Class Code RegisterThis register identifies the basic function of the device, a more

Datasheet, Volume 2 169Processor Configuration Registers 2.10.9 PBUSN—Primary Bus Number RegisterThis register identifies that this "virtual"

Datasheet, Volume 2 17Processor Configuration Registers 2.3 System Address MapThe processor supports 512 GB (39 bit) of addressable memory space and 6

Processor Configuration Registers170 Datasheet, Volume 22.10.12 IOBASE—I/O Base Address RegisterThis register controls the processor to PCI Express-G

Datasheet, Volume 2 171Processor Configuration Registers 2.10.14 SSTS—Secondary Status RegisterSSTS is a 16-bit status register that reports the occur

Processor Configuration Registers172 Datasheet, Volume 22.10.15 MBASE—Memory Base Address RegisterThis register controls the processor to PCI Express-

Datasheet, Volume 2 173Processor Configuration Registers 2.10.16 MLIMIT—Memory Limit Address RegisterThis register controls the processor to PCI Expre

Processor Configuration Registers174 Datasheet, Volume 22.10.17 PMBASE—Prefetchable Memory Base Address RegisterThis register in conjunction with the

Datasheet, Volume 2 175Processor Configuration Registers 2.10.18 PMLIMIT—Prefetchable Memory Limit Address RegisterThis register in conjunction with t

Processor Configuration Registers176 Datasheet, Volume 22.10.19 PMBASEU—Prefetchable Memory Base Address Upper RegisterThe functionality associated wi

Datasheet, Volume 2 177Processor Configuration Registers 2.10.20 PMLIMITU—Prefetchable Memory Limit Address Upper RegisterThe functionality associated

Processor Configuration Registers178 Datasheet, Volume 22.10.21 CAPPTR—Capabilities Pointer RegisterThe capabilities pointer provides the address offs

Datasheet, Volume 2 179Processor Configuration Registers 2.10.23 INTRPIN—Interrupt Pin RegisterThis register specifies which interrupt pin this device

Processor Configuration Registers18 Datasheet, Volume 2• Device 6, Function 0: (PCIe x4 Controller) — MBASE/MLIMIT – PCI Express port non-prefetchable

Processor Configuration Registers180 Datasheet, Volume 26RW 0bUncoreSecondary Bus Reset (SRESET)Setting this bit triggers a hot reset on the correspon

Datasheet, Volume 2 181Processor Configuration Registers 2.10.25 PM_CAPID—Power Management Capabilities RegisterB/D/F/Type: 0/6/0/PCIAddress Offset: 8

Processor Configuration Registers182 Datasheet, Volume 22.10.26 PM_CS—Power Management Control/Status RegisterB/D/F/Type: 0/6/0/PCIAddress Offset: 84–

Datasheet, Volume 2 183Processor Configuration Registers 1:0 RW 00b UncorePower State (PS)This field indicates the current power state of this device

Processor Configuration Registers184 Datasheet, Volume 22.10.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities RegisterThis capability is used to un

Datasheet, Volume 2 185Processor Configuration Registers 2.10.29 MSI_CAPID—Message Signaled Interrupts Capability ID RegisterWhen a device supports MS

Processor Configuration Registers186 Datasheet, Volume 22.10.31 MA—Message Address Register6:4 RW 000b UncoreMultiple Message Enable (MME)System softw

Datasheet, Volume 2 187Processor Configuration Registers 2.10.32 MD—Message Data Register2.10.33 PEG_CAPL—PCI Express-G Capability List RegisterThis r

Processor Configuration Registers188 Datasheet, Volume 22.10.34 PEG_CAP—PCI Express-G Capabilities RegisterThis register indicates PCI Express* device

Datasheet, Volume 2 189Processor Configuration Registers 2.10.36 DCTL—Device Control RegisterThis register provides control for PCI Express* device sp

Datasheet, Volume 2 19Processor Configuration Registers 2.3.1 Legacy Address RangeThis area is divided into the following address regions:• 0–640 KB –

Processor Configuration Registers190 Datasheet, Volume 22.10.37 DSTS—Device Status RegisterThis register reflects status corresponding to controls in

Datasheet, Volume 2 191Processor Configuration Registers 2.10.38 LCAP—Link Capabilities RegisterThis register indicates PCI Express* device-specific c

Processor Configuration Registers192 Datasheet, Volume 214:12 RO-V 100b UncoreL0s Exit Latency (L0SELAT)This field indicates the length of time this P

Datasheet, Volume 2 193Processor Configuration Registers 2.10.39 LCTL—Link Control RegisterThis register allows control of PCI Express* link.B/D/F/Typ

Processor Configuration Registers194 Datasheet, Volume 26RW 0bUncoreCommon Clock Configuration (CCC)0 = This component and the component at the opposi

Datasheet, Volume 2 195Processor Configuration Registers 2.10.40 LSTS—Link Status RegisterThis register indicates PCI Express* link status.B/D/F/Type:

Processor Configuration Registers196 Datasheet, Volume 22.10.41 SLOTCAP—Slot Capabilities RegisterNote: PCI Express* Hot-Plug is not supported on the

Datasheet, Volume 2 197Processor Configuration Registers 16:15 RW-O 00b UncoreSlot Power Limit Scale (SPLS)This field specifies the scale used for the

Processor Configuration Registers198 Datasheet, Volume 22.10.42 SLOTCTL—Slot Control RegisterNote: PCI Express* Hot-Plug is not supported on the proce

Datasheet, Volume 2 199Processor Configuration Registers 7:6 RO 00b UncoreReserved for Attention Indicator Control (AIC)If an Attention Indicator is i

2 Datasheet, Volume 2INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERW

Processor Configuration Registers20 Datasheet, Volume 22.3.1.1 DOS Range (0h–9_FFFFh)The DOS area is 640 KB (0000_0000h–0009_FFFFh) in size and is alw

Processor Configuration Registers200 Datasheet, Volume 22.10.43 SLOTSTS—Slot Status RegisterThis is a PCI Express* Slot related register.B/D/F/Type: 0

Datasheet, Volume 2 201Processor Configuration Registers 4RO 0bUncoreReserved for Command Completed (CC)If Command Completed notification is supported

Processor Configuration Registers202 Datasheet, Volume 22.10.44 RCTL—Root Control RegisterThis register allows control of PCI Express* Root Complex sp

Datasheet, Volume 2 203Processor Configuration Registers 2.11 PCI Device 6 Extended Configuration RegistersTable 2-14. PCI Device 6 Extended Configura

Processor Configuration Registers204 Datasheet, Volume 22.11.1 PVCCAP1—Port VC Capability Register 1This register describes the configuration of PCI E

Datasheet, Volume 2 205Processor Configuration Registers 2.11.3 PVCCTL—Port VC Control Register2.11.4 VC0RCAP—VC0 Resource Capability RegisterB/D/F/Ty

Processor Configuration Registers206 Datasheet, Volume 27:0 RO 01h UncorePort Arbitration Capability (PAC)Indicates types of Port Arbitration supporte

Datasheet, Volume 2 207Processor Configuration Registers 2.11.5 VC0RCTL—VC0 Resource Control RegisterThis register controls the resources associated w

Processor Configuration Registers208 Datasheet, Volume 22.11.6 VC0RSTS—VC0 Resource Status RegisterThis register reports the Virtual Channel specific

Datasheet, Volume 2 209Processor Configuration Registers 2.11.8 ESD—Element Self Description RegisterThis register provides information about the root

Datasheet, Volume 2 21Processor Configuration Registers Compatible SMRAM Address Range (A_0000h–B_FFFFh)When compatible SMM space is enabled, SMM-mode

Processor Configuration Registers210 Datasheet, Volume 22.11.9 LE1D—Link Entry 1 Description RegisterThis register provides the first part of a Link E

Datasheet, Volume 2 211Processor Configuration Registers 2.11.11 LE1AH—Link Entry 1 Address RegisterThis register provides the second part of a Link E

Processor Configuration Registers212 Datasheet, Volume 22.11.13 APICLIMIT—APIC Base Address Limit Register2.11.14 CMNRXERR—Common Rx Error RegisterB/D

Datasheet, Volume 2 213Processor Configuration Registers 2.11.15 PEGTST—PCI Express* Test Modes Register2.11.16 PEGUPDNCFG—PEG UPconfig/DNconfig Contr

Processor Configuration Registers214 Datasheet, Volume 22.11.17 BGFCTL3—BGF Control 3 RegisterB/D/F/Type: 0/6/0/MMRAddress Offset: D6C–D6FhReset Value

Datasheet, Volume 2 215Processor Configuration Registers 2.11.18 EQPRESET1_2—Equalization Preset 1/2 RegisterThis register contains coefficients for P

Processor Configuration Registers216 Datasheet, Volume 22.11.20 EQPRESET6_7—Equalization Preset 6/7 RegisterThis register contains coefficients for Pr

Datasheet, Volume 2 217Processor Configuration Registers 2.12 Direct Media Interface Base Address Registers (DMIBAR)Table 2-15. DMIBAR Register Addres

Processor Configuration Registers218 Datasheet, Volume 22.12.1 DMIVCECH—DMI Virtual Channel Enhanced Capability RegisterThis register indicates DMI Vi

Datasheet, Volume 2 219Processor Configuration Registers 2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1This register describes the configuration

Processor Configuration Registers22 Datasheet, Volume 22.3.2 Main Memory Address Range (1 MB – TOLUD)This address range extends from 1 MB to the top o

Processor Configuration Registers220 Datasheet, Volume 22.12.4 DMIPVCCTL—DMI Port VC Control Register2.12.5 DMIVC0RCAP—DMI VC0 Resource Capability Reg

Datasheet, Volume 2 221Processor Configuration Registers 2.12.6 DMIVC0RCTL—DMI VC0 Resource Control RegisterThis register controls the resources assoc

Processor Configuration Registers222 Datasheet, Volume 22.12.7 DMIVC0RSTS—DMI VC0 Resource Status RegisterThis register reports the Virtual Channel sp

Datasheet, Volume 2 223Processor Configuration Registers 2.12.9 DMIVC1RCTL—DMI VC1 Resource Control RegisterThis register controls the resources assoc

Processor Configuration Registers224 Datasheet, Volume 22.12.10 DMIVC1RSTS—DMI VC1 Resource Status RegisterThis register reports the Virtual Channel s

Datasheet, Volume 2 225Processor Configuration Registers 2.12.12 DMIVCPRCTL—DMI VCp Resource Control RegisterThis register controls the resources asso

Processor Configuration Registers226 Datasheet, Volume 22.12.13 DMIVCPRSTS—DMI VCp Resource Status RegisterThis register reports the Virtual Channel s

Datasheet, Volume 2 227Processor Configuration Registers 2.12.15 DMIVCMRCTL—DMI VCm Resource Control RegisterB/D/F/Type: 0/0/0/DMIBARAddress Offset: 3

Processor Configuration Registers228 Datasheet, Volume 22.12.16 DMIVCMRSTS—DMI VCm Resource Status Register2.12.17 DMIRCLDECH—DMI Root Complex Link De

Datasheet, Volume 2 229Processor Configuration Registers 2.12.18 DMIESD—DMI Element Self Description RegisterThis register provides information about

Datasheet, Volume 2 23Processor Configuration Registers 2.3.2.2 TSEGFor processor initiated transactions, the processor relies on correct programming

Processor Configuration Registers230 Datasheet, Volume 22.12.19 DMILE1D—DMI Link Entry 1 Description RegisterThis register provides the first part of

Datasheet, Volume 2 231Processor Configuration Registers 2.12.20 DMILE1A—DMI Link Entry 1 Address RegisterThis register provides the second part of a

Processor Configuration Registers232 Datasheet, Volume 22.12.22 DMILE2D—DMI Link Entry 2 Description RegisterThis register provides the first part of

Datasheet, Volume 2 233Processor Configuration Registers 2.12.23 DMILE2A—DMI Link Entry 2 Address RegisterThis register provides the second part of a

Processor Configuration Registers234 Datasheet, Volume 22.12.25 LCTL—Link Control RegisterThis register allows control of PCI Express* link.11:10 RO 1

Datasheet, Volume 2 235Processor Configuration Registers 2.12.26 LSTS—DMI Link Status RegisterThis register indicates DMI status.4RW 0bUncoreLink Disa

Processor Configuration Registers236 Datasheet, Volume 22.12.27 LCTL2—Link Control 2 RegisterB/D/F/Type: 0/0/0/DMIBARAddress Offset: 98–99hReset Value

Datasheet, Volume 2 237Processor Configuration Registers 9:7 RWS-V 000b PowergoodTransmit Margin (txmargin)This field controls the value of the non-de

Processor Configuration Registers238 Datasheet, Volume 22.12.28 LSTS2—Link Status 2 Register5RWS 0bPowergoodHardware Autonomous Speed Disable (HASD)Wh

Datasheet, Volume 2 239Processor Configuration Registers 2.13 MCHBAR Registers in Memory Controller—Channel 0 RegistersTable 2-16. MCHBAR Registers in

Processor Configuration Registers24 Datasheet, Volume 22.3.2.4 DRAM Protected Range (DPR)This protection range only applies to DMA accesses and GMADR

Processor Configuration Registers240 Datasheet, Volume 22.13.1 TC_DBP_C0—Timing of DDR – Bin Parameters RegisterThis register defines the BIN timing p

Datasheet, Volume 2 241Processor Configuration Registers 2.13.2 TC_RAP_C0—Timing of DDR – Regular Access Parameters RegisterThie register is for the r

Processor Configuration Registers242 Datasheet, Volume 22.13.3 SC_IO_LATENCY_C0—IO Latency configuration RegisterThis register identifies the I/O late

Datasheet, Volume 2 243Processor Configuration Registers 2.13.5 PM_PDWN_config_C0–Power-down Configuration RegisterThis register defines the power-dow

Processor Configuration Registers244 Datasheet, Volume 22.13.6 TC_RFP_C0—Refresh Parameters RegisterThis register provides the refresh parameters.2.13

Datasheet, Volume 2 245Processor Configuration Registers 2.14 MCHBAR Registers in Memory Controller – Channel 1 2.14.1 TC_DBP_C1—Timing of DDR – Bin P

Processor Configuration Registers246 Datasheet, Volume 22.14.2 TC_RAP_C1—Timing of DDR – Regular Access Parameters RegisterThis register provides the

Datasheet, Volume 2 247Processor Configuration Registers 2.14.3 SC_IO_LATENCY_C1—IO Latency configuration RegisterThis register identifies the I/O lat

Processor Configuration Registers248 Datasheet, Volume 22.14.4 PM_PDWN_config_C1—Power-down Configuration RegisterThis register defines the power-down

Datasheet, Volume 2 249Processor Configuration Registers 2.14.5 TC_RFP_C1—Refresh Parameters Register This register provides refresh parameters.B/D/F/

Datasheet, Volume 2 25Processor Configuration Registers 2.3.2.7 Intel® Management Engine (Intel® ME) UMA Intel ME (the AMT Intel Management Engine) ca

Processor Configuration Registers250 Datasheet, Volume 22.14.6 TC_RFTP_C1—Refresh Timing Parameters RegisterThie register provides refresh timing para

Datasheet, Volume 2 251Processor Configuration Registers 2.15 MCHBAR Registers in Memory Controller – Integrated Memory Peripheral Hub (IMPH)2.15.1 CR

Processor Configuration Registers252 Datasheet, Volume 22.15.2 CRDTCTL4—Credit Control 4 RegisterThis register will have the minimum Read Return Track

Datasheet, Volume 2 253Processor Configuration Registers 2.16 MCHBAR Registers in Memory Controller – Common2.16.1 MAD_CHNL—Address Decoder Channel Co

Processor Configuration Registers254 Datasheet, Volume 22.16.2 MAD_DIMM_ch0—Address Decode Channel 0 RegisterThis register defines channel characteris

Datasheet, Volume 2 255Processor Configuration Registers 2.16.3 MAD_DIMM_ch1—Address Decode Channel 1 RegisterThis register defines channel characteri

Processor Configuration Registers256 Datasheet, Volume 22.16.4 PM_SREF_config—Self Refresh Configuration RegisterThis is a self refresh mode control r

Datasheet, Volume 2 257Processor Configuration Registers 2.17 Memory Controller MMIO Registers Broadcast Group RegistersTable 2-20. Memory Controller

Processor Configuration Registers258 Datasheet, Volume 22.17.1 PM_PDWN_config—Power-down Configuration RegisterThis register defines the power-down (C

Datasheet, Volume 2 259Processor Configuration Registers 2.17.2 PM_CMD_PWR—Power Management Command Power RegisterThis register defines the power cont

Processor Configuration Registers26 Datasheet, Volume 22.3.3.1 APIC Configuration Space (FEC0_0000h – FECF_FFFFh)This range is reserved for APIC confi

Processor Configuration Registers260 Datasheet, Volume 22.18 Integrated Graphics VTd Remapping Engine RegistersTable 2-21. Integrated Graphics VTd Rem

Datasheet, Volume 2 261Processor Configuration Registers 2.18.1 VER_REG—Version RegisterThis register reports the architecture version supported. Back

Processor Configuration Registers262 Datasheet, Volume 22.18.2 CAP_REG—Capability RegisterThis register reports general remapping hardware capabilitie

Datasheet, Volume 2 263Processor Configuration Registers 33:24 RO 020h UncoreFault-recording Register offset (FRO) This field specifies the location t

Processor Configuration Registers264 Datasheet, Volume 212:8 RO 00010b UncoreSupported Adjusted Guest Address Widths (SAGAW) This 5-bit field indicate

Datasheet, Volume 2 265Processor Configuration Registers 4RO 0bUncoreRequired Write-Buffer Flushing (RWBF) 0 = No write-buffer flushing is needed to e

Processor Configuration Registers266 Datasheet, Volume 22.18.3 ECAP_REG—Extended Capability RegisterThis Register reports remapping hardware extended

Datasheet, Volume 2 267Processor Configuration Registers 2.18.4 GCMD_REG—Global Command RegisterThis register controls remapping hardware. If multiple

Processor Configuration Registers268 Datasheet, Volume 230 WO 0b UncoreSet Root Table Pointer (SRTP) Software sets this field to set/update the root-e

Datasheet, Volume 2 269Processor Configuration Registers 27 RO 0b UncoreWrite Buffer Flush (WBF) This bit is valid only for implementations requiring

Datasheet, Volume 2 27Processor Configuration Registers Memory requests to this range would then be forwarded to the PCI Express port. This mode is in

Processor Configuration Registers270 Datasheet, Volume 224 WO 0b UncoreSet Interrupt Remap Table Pointer (SIRTP) This field is valid only for implemen

Datasheet, Volume 2 271Processor Configuration Registers 2.18.5 GSTS_REG—Global Status RegisterThis register reports general remapping hardware status

Processor Configuration Registers272 Datasheet, Volume 22.18.6 RTADDR_REG—Root-Entry Table Address RegisterThis register providing the base address of

Datasheet, Volume 2 273Processor Configuration Registers 2.18.7 CCMD_REG—Context Command RegisterThis register manages context cache. The act of writi

Processor Configuration Registers274 Datasheet, Volume 260:59 RO-V 1h UncoreContext Actual Invalidation Granularity (CAIG) Hardware reports the granul

Datasheet, Volume 2 275Processor Configuration Registers 2.18.8 FSTS_REG—Fault Status RegisterThis register indicates the various error status.B/D/F/T

Processor Configuration Registers276 Datasheet, Volume 22 RO 0b UncoreAdvanced Fault Overflow (AFO) Hardware sets this field to indicate advanced faul

Datasheet, Volume 2 277Processor Configuration Registers 2.18.9 FECTL_REG—Fault Event Control RegisterThis register specifies the fault event interrup

Processor Configuration Registers278 Datasheet, Volume 22.18.10 FEDATA_REG—Fault Event Data RegisterThis register specifies the interrupt message data

Datasheet, Volume 2 279Processor Configuration Registers 2.18.13 AFLOG_REG—Advanced Fault Log RegisterThis register specifies the base address of the

Processor Configuration Registers28 Datasheet, Volume 2Top of Upper Usable DRAM (TOUUD)The Top of Upper Usable Dram (TOUUD) register reflects the tota

Processor Configuration Registers280 Datasheet, Volume 22.18.14 PMEN_REG—Protected Memory Enable RegisterThis register enables the DMA-protected memor

Datasheet, Volume 2 281Processor Configuration Registers 2.18.15 PLMBASE_REG—Protected Low-Memory Base RegisterThis register sets up the base address

Processor Configuration Registers282 Datasheet, Volume 22.18.16 PLMLIMIT_REG—Protected Low-Memory Limit RegisterThis register sets up the limit addres

Datasheet, Volume 2 283Processor Configuration Registers 2.18.17 PHMBASE_REG—Protected High-Memory Base RegisterThis register sets up the base address

Processor Configuration Registers284 Datasheet, Volume 22.18.18 PHMLIMIT_REG—Protected High-Memory Limit RegisterThis register sets up the limit addre

Datasheet, Volume 2 285Processor Configuration Registers 2.18.19 IQH_REG—Invalidation Queue Head RegisterThis register indicates the invalidation queu

Processor Configuration Registers286 Datasheet, Volume 22.18.21 IQA_REG—Invalidation Queue Address RegisterThis register configures the base address a

Datasheet, Volume 2 287Processor Configuration Registers 2.18.23 IECTL_REG—Invalidation Event Control RegisterThis register specifies the invalidation

Processor Configuration Registers288 Datasheet, Volume 22.18.24 IEDATA_REG—Invalidation Event Data RegisterThis register specifies the Invalidation Ev

Datasheet, Volume 2 289Processor Configuration Registers 2.18.26 IEUADDR_REG—Invalidation Event Upper Address RegisterThis register specifies the Inva

Datasheet, Volume 2 29Processor Configuration Registers 2.3.4.2 Indirect Accesses to MCHBAR RegistersSimilar to prior chipsets, MCHBAR registers can b

Processor Configuration Registers290 Datasheet, Volume 22.18.28 IVA_REG—Invalidate Address RegisterThis register provides the DMA address whose corres

Datasheet, Volume 2 291Processor Configuration Registers 2.18.29 IOTLB_REG—IOTLB Invalidate RegisterThis register invalidates IOTLB. The act of writin

Processor Configuration Registers292 Datasheet, Volume 258:57 RO-V 1h UncoreIOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granular

Datasheet, Volume 2 293Processor Configuration Registers 2.18.30 FRCDL_REG—Fault Recording Low RegisterThis register records fault information when pr

Processor Configuration Registers294 Datasheet, Volume 22.18.31 FRCDH_REG—Fault Recording High RegisterThis register records fault information when pr

Datasheet, Volume 2 295Processor Configuration Registers 2.18.32 VTPOLICY—DMA Remap Engine Policy Control RegisterThis register contains all the polic

Processor Configuration Registers296 Datasheet, Volume 22.19 PCU MCHBAR RegistersTable 2-22. PCU MCHBAR Register Address Map Address OffsetRegister Sy

Datasheet, Volume 2 297Processor Configuration Registers 2.19.1 MEM_TRML_ESTIMATION_CONFIG—Memory Thermal Estimation Configuration RegisterThis regis

Processor Configuration Registers298 Datasheet, Volume 22.19.2 MEM_TRML_THRESHOLDS_CONFIG—Memory Thermal Thresholds Configuration RegisterThis regist

Datasheet, Volume 2 299Processor Configuration Registers 2.19.3 MEM_TRML_STATUS_REPORT—Memory Thermal Status Report RegisterThis register reports the

Datasheet, Volume 2 3Contents1Introduction...

Processor Configuration Registers30 Datasheet, Volume 22.3.4.5 Programming ModelThe memory boundaries of interest are:• Bottom of Logical Address Rema

Processor Configuration Registers300 Datasheet, Volume 22.19.4 MEM_TRML_TEMPERATURE_REPORT—Memory Thermal Temperature Report RegisterThis register is

Datasheet, Volume 2 301Processor Configuration Registers 2.19.6 GT_PERF_STATUS—GT Performance Status RegisterThis register provides the P-state encodi

Processor Configuration Registers302 Datasheet, Volume 22.19.8 RP_STATE_CAP—RP State Capability RegisterThis register contains the maximum base freque

Datasheet, Volume 2 303Processor Configuration Registers 20:19 RW 00000000h Reserved (RSVD)18 RW 00000000h Uncorepp1_clipped_pl1 Set if the PP1 (GT) f

Processor Configuration Registers304 Datasheet, Volume 22.19.10 PCU_MMIO_FREQ_CLIPPING_CAUSE_LOG RegisterThis register is the log of the frequency cli

Datasheet, Volume 2 305Processor Configuration Registers 13 RW 00000000h Uncorepp0_clipped_non_turboSet if the PP0 (IA) frequency requested by OS was

Processor Configuration Registers306 Datasheet, Volume 22.19.11 SSKPD—Sticky Scratchpad Data RegisterThis register holds 64 writable bits with no func

Datasheet, Volume 2 307Processor Configuration Registers 13:8 RWS 000000b PowergoodSelf Refresh and MDLL Latency Time (WM1) This field provides the nu

Processor Configuration Registers308 Datasheet, Volume 22.20 PXPEPBAR Registers 2.20.1 EPVC0RCTL—EP VC 0 Resource Control Register This register contr

Datasheet, Volume 2 309Processor Configuration Registers 2.21 Default PEG/DMI VTd Remapping Engine RegistersTable 2-24. Default PEG/DMI VTd Remapping

Datasheet, Volume 2 31Processor Configuration Registers 2.3.4.5.1 Case 1 – Less than 4 GB of Physical Memory (no remap)• Populated Physical Memory = 2

Processor Configuration Registers310 Datasheet, Volume 22.21.1 VER_REG—Version RegisterThis register reports the architecture version supported. Backw

Datasheet, Volume 2 311Processor Configuration Registers 2.21.2 CAP_REG—Capability RegisterThis register reports general remapping hardware capabiliti

Processor Configuration Registers312 Datasheet, Volume 233:24 RO 020h UncoreFault-recording Register offset (FRO) This field specifies the location to

Datasheet, Volume 2 313Processor Configuration Registers 12:8 RO 00010b UncoreSupported Adjusted Guest Address Widths (SAGAW) This 5-bit field indicat

Processor Configuration Registers314 Datasheet, Volume 24RO 0bUncoreRequired Write-Buffer Flushing (RWBF) 0 = Indicates no write-buffer flushing is ne

Datasheet, Volume 2 315Processor Configuration Registers 2.21.3 ECAP_REG—Extended Capability RegisterThis register reports remapping hardware extended

Processor Configuration Registers316 Datasheet, Volume 22.21.4 GCMD_REG—Global Command RegisterThis register controls remapping hardware. If multiple

Datasheet, Volume 2 317Processor Configuration Registers 30 WO 0b UncoreSet Root Table Pointer (SRTP) Software sets this field to set/update the root-

Processor Configuration Registers318 Datasheet, Volume 227 RO 0b UncoreWrite Buffer Flush (WBF) This bit is valid only for implementations requiring w

Datasheet, Volume 2 319Processor Configuration Registers 24 WO 0b UncoreSet Interrupt Remap Table Pointer (SIRTP) This field is valid only for impleme

Processor Configuration Registers32 Datasheet, Volume 22.3.4.5.2 Case 2 – Greater than 4 GB of Physical MemoryIn this case the amount of memory remapp

Processor Configuration Registers320 Datasheet, Volume 22.21.5 GSTS_REG—Global Status RegisterThis register reports general remapping hardware status.

Datasheet, Volume 2 321Processor Configuration Registers 2.21.6 RTADDR_REG—Root-Entry Table Address RegisterThis register provides the base address of

Processor Configuration Registers322 Datasheet, Volume 22.21.7 CCMD_REG—Context Command RegisterThis register manages context cache. The act of writin

Datasheet, Volume 2 323Processor Configuration Registers 60:59 RO-V 0h UncoreContext Actual Invalidation Granularity (CAIG) Hardware reports the granu

Processor Configuration Registers324 Datasheet, Volume 22.21.8 FSTS_REG—Fault Status RegisterThis register indicates the various error status.B/D/F/Ty

Datasheet, Volume 2 325Processor Configuration Registers 2RO 0b UncoreAdvanced Fault Overflow (AFO) Hardware sets this field to indicate advanced faul

Processor Configuration Registers326 Datasheet, Volume 22.21.9 FECTL_REG—Fault Event Control RegisterThis register specifies the fault event interrupt

Datasheet, Volume 2 327Processor Configuration Registers 2.21.10 FEDATA_REG—Fault Event Data RegisterThis register specifies the interrupt message dat

Processor Configuration Registers328 Datasheet, Volume 22.21.13 AFLOG_REG—Advanced Fault Log RegisterThis register specifies the base address of the m

Datasheet, Volume 2 329Processor Configuration Registers 2.21.14 PMEN_REG—Protected Memory Enable RegisterThis register enables the DMA-protected memo

Datasheet, Volume 2 33Processor Configuration Registers Example: 5 GB of Physical Memory, with 1 GB allocated to Memory Mapped IO• Populated Physical

Processor Configuration Registers330 Datasheet, Volume 22.21.15 PLMBASE_REG—Protected Low-Memory Base RegisterThis register sets up the base address o

Datasheet, Volume 2 331Processor Configuration Registers 2.21.16 PLMLIMIT_REG—Protected Low-Memory Limit RegisterThis register sets up the limit addre

Processor Configuration Registers332 Datasheet, Volume 22.21.17 PHMBASE_REG—Protected High-Memory Base RegisterThis register sets up the base address

Datasheet, Volume 2 333Processor Configuration Registers 2.21.18 PHMLIMIT_REG—Protected High-Memory Limit RegisterThis register sets up the limit addr

Processor Configuration Registers334 Datasheet, Volume 22.21.19 IQH_REG—Invalidation Queue Head RegisterThis register indicates the invalidation queue

Datasheet, Volume 2 335Processor Configuration Registers 2.21.21 IQA_REG—Invalidation Queue Address RegisterThis register configures the base address

Processor Configuration Registers336 Datasheet, Volume 22.21.22 ICS_REG—Invalidation Completion Status RegisterThis register reports completion status

Datasheet, Volume 2 337Processor Configuration Registers 2.21.24 IEDATA_REG—Invalidation Event Data RegisterThis register specifies the Invalidation E

Processor Configuration Registers338 Datasheet, Volume 22.21.25 IEADDR_REG—Invalidation Event Address RegisterThis register specifies the Invalidation

Datasheet, Volume 2 339Processor Configuration Registers 2.21.27 IRTA_REG—Interrupt Remapping Table Address RegisterThis register provides the base ad

Processor Configuration Registers34 Datasheet, Volume 2MSI Interrupts At fixed address below 4 GBGMADR 64 bit BARs GTTMMADR 64 bit BARs MBASE/MLIMITPX

Processor Configuration Registers340 Datasheet, Volume 22.21.28 IVA_REG—Invalidate Address RegisterThis register provides the DMA address whose corres

Datasheet, Volume 2 341Processor Configuration Registers 2.21.29 IOTLB_REG—IOTLB Invalidate RegisterThis register invalidates IOTLB. The act of writin

Processor Configuration Registers342 Datasheet, Volume 2§ §58:57 RO-V 0h UncoreIOTLB Actual Invalidation Granularity (IAIG) Hardware reports the granu

Datasheet, Volume 2 35Processor Configuration Registers 2.3.5 PCI Express* Configuration Address SpacePCIEXBAR is located in Device 0 configuration sp

Processor Configuration Registers36 Datasheet, Volume 22.3.7 Graphics Memory Address RangesThe integrated memory controller can be programmed to direc

Datasheet, Volume 2 37Processor Configuration Registers 2.3.8 System Management Mode (SMM)The Core handles all SMM mode transaction routing. Also, the

Processor Configuration Registers38 Datasheet, Volume 22.3.11 I/O Address SpaceThe system agent generates either DMI Interface or PCI Express bus cycl

Datasheet, Volume 2 39Processor Configuration Registers The processor also forwards accesses to the Legacy VGA I/O ranges according to the settings in

4 Datasheet, Volume 22.5.10 CAPPTR—Capabilities Pointer Register ...542.5.11 PXPEPBAR—PCI Express* Eg

Processor Configuration Registers40 Datasheet, Volume 2DMI Interface Accesses to the processor that Cross Device BoundariesThe processor does not supp

Datasheet, Volume 2 41Processor Configuration Registers e. Internal Graphics GMADR writes and GMADR reads are not supported.4. VCm accessesa. See DMI2

Processor Configuration Registers42 Datasheet, Volume 22.3.13.2 PCI Express* Interface Decode RulesAll “SNOOP semantic” PCI Express transactions are k

Datasheet, Volume 2 43Processor Configuration Registers 2.3.13.3 Legacy VGA and I/O Range Decode RulesThe legacy 128 KB VGA memory range 000A_0000h–00

Processor Configuration Registers44 Datasheet, Volume 2Accesses to the VGA memory range are directed to IGD depend on the configuration. The configura

Datasheet, Volume 2 45Processor Configuration Registers For regions mapped outside of the IGD (or if IGD is disabled), the legacy VGA memory range A00

Processor Configuration Registers46 Datasheet, Volume 2MDA Present (MDAP): This bit works with the VGA Enable bit in the BCTRL register of Device 1 to

Datasheet, Volume 2 47Processor Configuration Registers 2.5 PCI Device 0 Function 0 Configuration Space RegistersTable 2-8. PCI Device 0, Function 0 C

Processor Configuration Registers48 Datasheet, Volume 22.5.1 VID—Vendor Identification RegisterThis register combined with the Device Identification r

Datasheet, Volume 2 49Processor Configuration Registers 2.5.2 DID—Device Identification RegisterThis register combined with the Vendor Identification

Datasheet, Volume 2 52.6.26 PM_CS—Power Management Control/Status Register ... 1052.6.27 SS_CAPID—Subsystem ID and Vendor ID

Processor Configuration Registers50 Datasheet, Volume 22.5.4 PCISTS—PCI Status RegisterThis status register reports the occurrence of error events on

Datasheet, Volume 2 51Processor Configuration Registers 14 RW1C 0b UncoreSignaled System Error (SSE) This bit is set to 1 when Device 0 generates an S

Processor Configuration Registers52 Datasheet, Volume 22.5.5 RID—Revision Identification RegisterThis register contains the revision number of Device

Datasheet, Volume 2 53Processor Configuration Registers 2.5.7 HDR—Header Type RegisterThis register identifies the header layout of the configuration

Processor Configuration Registers54 Datasheet, Volume 22.5.10 CAPPTR—Capabilities Pointer RegisterThe CAPPTR provides the offset that is the pointer t

Datasheet, Volume 2 55Processor Configuration Registers 2.5.12 MCHBAR—Host Memory Mapped Register Range Base RegisterThis is the base address for the

Processor Configuration Registers56 Datasheet, Volume 29:8 RW-L 0h UncoreGTT Graphics Memory Size (GGMS) This field is used to select the amount of Ma

Datasheet, Volume 2 57Processor Configuration Registers 2.5.14 DEVEN—Device Enable RegisterThis register allows for enabling/disabling of PCI devices

Processor Configuration Registers58 Datasheet, Volume 27RW-L 1b UncoreDevice 4 Enable (D4EN) 0 = Bus 0 Device 4 is disabled and not visible.1 = Bus 0

Datasheet, Volume 2 59Processor Configuration Registers 2.5.15 PAVPC—Protected Audio Video Path Control RegisterAll the bits in this register are lock

6 Datasheet, Volume 22.8.13 SVID2—Subsystem Vendor Identification Register...1562.8.14 SID2—Subsystem Identification Re

Processor Configuration Registers60 Datasheet, Volume 22.5.17 PCIEXBAR—PCI Express* Register Range Base Address RegisterThis is the base address for t

Datasheet, Volume 2 61Processor Configuration Registers 27 RW-V 0b Uncore128 MB Base Address Mask (ADMSK128) This bit is either part of the PCI Expres

Processor Configuration Registers62 Datasheet, Volume 22.5.18 DMIBAR—Root Complex Register Range Base Address RegisterThis is the base address for the

Datasheet, Volume 2 63Processor Configuration Registers 2.5.19 MESEG_BASE—Intel® Management Engine Base Address RegisterThis register determines the B

Processor Configuration Registers64 Datasheet, Volume 22.5.20 MESEG_MASK—Intel® Management Engine Limit Address RegisterThis register determines the M

Datasheet, Volume 2 65Processor Configuration Registers 2.5.21 PAM0—Programmable Attribute Map 0 RegisterThis register controls the read, write and sh

Processor Configuration Registers66 Datasheet, Volume 22.5.22 PAM1—Programmable Attribute Map 1 RegisterThis register controls the read, write and sha

Datasheet, Volume 2 67Processor Configuration Registers 2.5.23 PAM2—Programmable Attribute Map 2 RegisterThis register controls the read, write and sh

Processor Configuration Registers68 Datasheet, Volume 22.5.24 PAM3—Programmable Attribute Map 3 RegisterThis register controls the read, write and sha

Datasheet, Volume 2 69Processor Configuration Registers 2.5.25 PAM4—Programmable Attribute Map 4 RegisterThis register controls the read, write and sh

Datasheet, Volume 2 72.10.44 RCTL—Root Control Register... 2022.10.45 LCAP2—Link Capabilit

Processor Configuration Registers70 Datasheet, Volume 22.5.26 PAM5—Programmable Attribute Map 5 RegisterThis register controls the read, write and sha

Datasheet, Volume 2 71Processor Configuration Registers 2.5.27 PAM6—Programmable Attribute Map 6 RegisterThis register controls the read, write and sh

Processor Configuration Registers72 Datasheet, Volume 22.5.28 LAC—Legacy Access Control RegisterThis 8-bit register controls steering of MDA cycles an

Datasheet, Volume 2 73Processor Configuration Registers 2RW 0bUncorePEG12 MDA Present (MDAP12) This bit works with the VGA Enable bits in the BCTRL re

Processor Configuration Registers74 Datasheet, Volume 21RW 0bUncorePEG11 MDA Present (MDAP11) This bit works with the VGA Enable bits in the BCTRL reg

Datasheet, Volume 2 75Processor Configuration Registers 0RW 0bUncorePEG10 MDA Present (MDAP10) This bit works with the VGA Enable bits in the BCTRL re

Processor Configuration Registers76 Datasheet, Volume 22.5.29 REMAPBASE—Remap Base Address RegisterB/D/F/Type: 0/0/0/PCIAddress Offset: 90–97hReset Va

Datasheet, Volume 2 77Processor Configuration Registers 2.5.30 REMAPLIMIT—Remap Limit Address Register2.5.31 TOM—Top of Memory RegisterThis Register c

Processor Configuration Registers78 Datasheet, Volume 22.5.32 TOUUD—Top of Upper Usable DRAM RegisterThis 64 bit register defines the Top of Upper Usa

Datasheet, Volume 2 79Processor Configuration Registers 2.5.33 BDSM—Base Data of Stolen Memory RegisterThis register contains the base address of grap

8 Datasheet, Volume 22.13.3 SC_IO_LATENCY_C0—IO Latency configuration Register ...2422.13.4 TC_SRFTP_C0–Self Refresh Timing Para

Processor Configuration Registers80 Datasheet, Volume 22.5.35 TSEGMB—TSEG Memory Base RegisterThis register contains the base address of TSEG DRAM mem

Datasheet, Volume 2 81Processor Configuration Registers 2.5.37 SKPD—Scratchpad Data RegisterThis register holds 32 writable bits with no functionality

Processor Configuration Registers82 Datasheet, Volume 22.5.38 CAPID0_A—Capabilities A RegisterThis register control of bits in this register are only

Datasheet, Volume 2 83Processor Configuration Registers 2RO-FW0bUncoreIA Overclocking Enabled by DSKU (OC_ENABLED_DSKU)The default constant (non-fuse)

Processor Configuration Registers84 Datasheet, Volume 22.5.39 CAPID0_B—Capabilities B RegisterControl of bits in this register are only required for c

Datasheet, Volume 2 85Processor Configuration Registers 11 RO-FW 0b Reserved (RSVD)10:8 RO-FW 000b Reserved (RSVD)7RO-FW 0b Reserved (RSVD)6:4 RO-FW 0

Processor Configuration Registers86 Datasheet, Volume 22.6 PCI Device 1 Function 0–2 Configuration Space RegistersTable 2-9. PCI Device 1 Function 0–2

Datasheet, Volume 2 87Processor Configuration Registers 2.6.1 VID—Vendor Identification RegisterThis register, combined with the Device Identification

Processor Configuration Registers88 Datasheet, Volume 22.6.2 DID—Device Identification RegisterThis register combined with the Vendor Identification r

Datasheet, Volume 2 89Processor Configuration Registers 8RW 0bUncoreSERR# Message Enable (SERRE)This bit controls the root port's SERR# messaging

Datasheet, Volume 2 92.18.30 FRCDL_REG—Fault Recording Low Register... 2932.18.31 FRCDH_REG—Fault Recording Hi

Processor Configuration Registers90 Datasheet, Volume 22.6.4 PCISTS—PCI Status RegisterThis register reports the occurrence of error conditions associ

Datasheet, Volume 2 91Processor Configuration Registers 12 RO 0b UncoreReceived Target Abort Status (RTAS)This bit is set when a Requester receives a

Processor Configuration Registers92 Datasheet, Volume 22.6.5 RID—Revision Identification RegisterThis register contains the revision number of the pro

Datasheet, Volume 2 93Processor Configuration Registers 2.6.8 HDR—Header Type RegisterThis register identifies the header layout of the configuration

Processor Configuration Registers94 Datasheet, Volume 22.6.11 SUBUSN—Subordinate Bus Number RegisterThis register identifies the subordinate bus (if a

Datasheet, Volume 2 95Processor Configuration Registers 2.6.12 IOBASE—I/O Base Address RegisterThis register controls the processor to PCI Express-G I

Processor Configuration Registers96 Datasheet, Volume 22.6.14 SSTS—Secondary Status RegisterSSTS is a 16-bit status register that reports the occurren

Datasheet, Volume 2 97Processor Configuration Registers 2.6.15 MBASE—Memory Base Address RegisterThis register controls the processor to PCI Express-G

Processor Configuration Registers98 Datasheet, Volume 22.6.16 MLIMIT—Memory Limit Address RegisterThis register controls the processor to PCI Express-

Datasheet, Volume 2 99Processor Configuration Registers 2.6.17 PMBASE—Prefetchable Memory Base Address RegisterThis register in conjunction with the c