Intel A2Y15AV Ficha Técnica descarregar pdf (Página 147)

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Datasheet, Volume 2 147

Processor Configuration Registers

5:2 RW 0h Uncore

Bypass Coefficients During Phase 3 (BYPCOEFPH3)

Bit [0]: Controls the value of bit 7 in Symbol 6 of EQ TS1s during

"Bypass Phase 3 Adaptation"

1 = use preset

0 = use coefficients

The preset is defined by the per-lane DCTP field in

EQCTL register. Coefficient values are defined within the

appropriate EQPRESET* register, using DCTP as an

index.

Bits [3:1]: Undefined

1RW 0bUncore

Bypass Phase 3 Adaptation FSM (BYPADFSM)

When set, when Phase 3 is entered, “bypass” coefficients will be

sent to the link partner. When the coefficients are accepted by

the link partner, no adaptation will be done, and Phase 3 will be

complete.

This bit needs to be set before phase 3 start.

0RO 0h Reserved (RSVD)

B/D/F/Type: 0/1/0/MMR

Address Offset: DD8–DDBh

Reset Value: F9404400h

Access: RW

Size: 32 bits

BIOS Optimal Default 0h

Bit Access

Reset

Value

RST/

PWR

Description

1 2 ... 142 143 144 145 146 147 148 149 150 151 152 ... 341 342

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