Intel A2Y15AV Ficha Técnica descarregar pdf (Página 60)

Processor Configuration Registers

60 Datasheet, Volume 2

2.5.17 PCIEXBAR—PCI Express* Register Range Base Address

This is the base address for the PCI Express configuration space. This window of

addresses contains the 4 KB of configuration space for each PCI Express device that

can potentially be part of the PCI Express Hierarchy associated with the Uncore. There

is no actual physical memory within this window of up to 256 MB that can be

addressed. The actual size of this range is determined by a field in this register.

Each PCI Express Hierarchy requires a PCI Express BASE register. The Uncore supports

one PCI Express Hierarchy. The region reserved by this register does not alias to any

PCI2.3 compliant memory mapped space. For example, the range reserved for

MCHBAR is outside of PCIEXBAR space.

On reset, this register is disabled and must be enabled by writing a 1 to the enable field

in this register. This base address shall be assigned on a boundary consistent with the

number of buses (defined by the length field in this register), above TOLUD and still

within 39-bit addressable memory space.

The PCI Express Base Address cannot be less than the maximum address written to the

Top of physical memory register (TOLUD). Software must ensure that these ranges do

not overlap with known ranges located above TOLUD.

Software must ensure that the sum of the length of the enhanced configuration region

+ TOLUD + any other known ranges reserved above TOLUD is not greater than the 39-

bit addessable limit of 512 GB. In general, system implementation and the number of

PCI/PCI Express/PCI-X buses supported in the hierarchy will dictate the length of the

region.

All the bits in this register are locked in Intel TXT mode.

B/D/F/Type: 0/0/0/PCI

Address Offset: 60–67h

Reset Value: 0000000000000000h

Access: RW, RW-V

Size: 64 bits

BIOS Optimal Default 000000000000h

Bit Access

Reset

Value

RST/

PWR

Description

63:39 RO 0h Reserved (RSVD)

38:28 RW 000h Uncore

PCI Express* Base Address (PCIEXBAR)

This field corresponds to bits 38:28 of the base address for PCI

Express enhanced configuration space. BIOS will program this

address space. The size of the range is defined by bits 2:1 of this

This Base address shall be assigned on a boundary consistent

with the number of buses (defined by the Length field in this

memory space. The address bits decoded depend on the length

of the region defined by this register.

This register is locked by Intel TXT.

The address used to access the PCI Express configuration space

for a specific device can be determined as follows:

PCI Express Base Address + Bus Number * 1MB + Device

Number * 32 KB + Function Number * 4 KB

This address is the beginning of the 4 KB space that contains

both the PCI compatible configuration space and the PCI Express

extended configuration space.

1 2 ... 55 56 57 58 59 60 61 62 63 64 65 ... 341 342

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Summit FRBW52D Handbuch (31 Seiten)

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Inhaltsverzeichnis

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Table of Contents

Description of Models

IMPORTANT SAFEGUARDS

- SAVE THESE INSTRUCTIONS

INSTALLATION

OPERATION

The Upper Warming Cabinet

CLEANING AND MAINTENANCE

WIRING DIAGRAM

TROUBLESHOOTING

LIMITED WARRANTY

Introduction

Table des matières

Description des Modèles

Installation

Fonctionnement

Nettoyage et entretien

Filtre à peluches

Temps d'arrêt prolongé

Entretien préventif

MODÈLES :

Dépannage

Notes

Garantie limitée

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