Intel 386 Manual do Utilizador descarregar pdf (Página 627)

100

101

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL

D-62

D.63 SSIOTBUF

D.64 TBR

Transmit Holding Buffer

SSIOTBUF

(read/write)

Expanded Addr:

ISA Addr:

Reset State:

F480H

—

0000H

15 8

TB15 TB14 TB13 TB12 TB11 TB10 TB9 TB8

7 0

TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0

Bit

Number

Bit

Mnemonic

Function

15–0 TB15:0 Transmit Buffer Bits:

These bits make up the next data word to be transmitted. The control

logic loads this word into the transmit shift register. The transmit shift

The word is transmitted out starting with the most-significant bit (TB15).

Transmit Buffer

TBR0, TBR1

(write only)

Expanded Addr:

ISA Addr:

Reset State:

TBR0 TBR1

F4F8H F8F8H

03F8H 02F8H

XXH XXH

7 0

TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0

Bit

Number

Bit

Mnemonic

Function

7–0 TB7:0 Transmit Buffer Bits:

These bits make up the next data word to be transmitted. The transmitter

loads this word into the transmit shift register. The transmit shift register

then shifts the bits out, along with the asynchronous communication bits

(start, stop, and parity). The data bits are shifted out least-significant bit

(TB0) first.

NOTE: The transmit buffer register shares an address port with other SIO registers. You must clear

bit 7 (DLAB) of LCR

before you can write to the transmit buffer register.

1 2 ... 622 623 624 625 626 627 628 629 630 631 632 ... 690 691

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Intel 386 Manual do Utilizador Página 627

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