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100

101

D-51

SYSTEM REGISTER QUICK REFERENCE

D.49 PWRCON

Power Control Register

PWRCON

(read/write)

Expanded Addr:

ISA Addr:

Reset State:

F800H

—

00H

7 0

— — — — WDTRDY HSREADY PC1 PC0

Bit

Number

Bit

Mnemonic

Function

7–4 — Reserved. These bits are undefined; for compatibility with future devices,

do not modify these bits.

3 WDTRDY Watch Dog Timer Ready:

0 = An external READY must be generated to terminate the cycle when

the WDT times out in Bus Monitor Mode.

1 = Internal logic generates READY# to terminate the cycle when the

WDT times out in Bus Monitor Mode.

2 HSREADY Halt/Shutdown Ready:

0 = An external ready must be generated to terminate a HALT/Shutdown

cycle.

1 = Internal logic generates READY# to terminate a HALT/Shutdown

cycle.

1–0 PC1:0 Power Control:

Program these bits, then execute a HALT instruction. The device enters

the programmed mode when READY# (internal or external) terminates

the halt bus cycle. When these bits have equal values, the HALT

instruction causes a normal halt and the device remains in active mode.

PC1 PC0

0 0 active mode

1 0 idle mode

01powerdown mode

1 1 active mode

1 2 ... 611 612 613 614 615 616 617 618 619 620 621 ... 690 691

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