Intel 386 Manual do Utilizador Página 1

Intel386™ EXEmbedded MicroprocessorUser’s ManualIntel386™ EXTBEmbeddedMicroprocessorIntel386™ EXTCEmbeddedMicroprocessor

ixCONTENTS12.2.4 Bus Control Arbitration ...12-912.2.5 Ending

5-27DEVICE CONFIGURATIONFigure 5-18. Port 3 Configuration Register (P3CFG)Port 3 ConfigurationP3CFG(read/write)Expanded Addr:ISA Addr:Reset State:F824

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-285.4 DEVICE CONFIGURATION PROCEDUREBefore configuring the microprocessor, make the following sele

5-29DEVICE CONFIGURATION— Counter 2: Clock input is on-chip programmable clock (PSCLK); no signals connected to package pins• DMA Unit:— Not Used• Asy

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-30Table 5-4. Example Pin Configuration RegistersBit # P1CFG Value Bit # P2CFG Value Bit # P3CFG Va

5-31DEVICE CONFIGURATIONTable 5-5. Example DMACFG Configuration Register Bit # DMACFG Value7 0 = Enables DACK1# at chip pin 11 = Disables DACK1# at ch

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-32Table 5-6. Example TMRCFG Configuration RegisterBit # TMRCFG Value7 0 = All clock inputs enabled

5-33DEVICE CONFIGURATIONTable 5-7. Example INTCFG Configuration RegisterTable 5-8. Example SIOCFG Configuration RegisterBit # INTCFG Value7 0 = CAS2:0

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-34Table 5-9. Pin Configuration Register Design WoksheetBit # P1CFG Value Bit # P2CFG Value Bit # P

5-35DEVICE CONFIGURATIONTable 5-10. DMACFG Register Design Worksheet Bit # DMACFG Value7 0 = Enables DACK1# at chip pin1 = Disables DACK1# at chip pin

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-36Table 5-11. TMRCFG Register Design WorksheetBit # TMRCFG Value7 0 = All clock inputs enabled1 =

Intel386™ EX MICROPROCESSOR USER’S MANUALx13.2.3 Receiver ...

5-37DEVICE CONFIGURATIONTable 5-12. INTCFG Register Design WorksheetTable 5-13. SIOCFG Register Design WorksheetBit # INTCFG Value7 0 = CAS2:0 disable

6BUS INTERFACE UNIT

6-1CHAPTER 6BUS INTERFACE UNITThe processor communicates with memory, I/O, and other devices through bus operations. Ad-dress, data, status, and contr

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-2• Data status pins indicate that data is available on the data bus for a write (WR#) or that the

6-3BUS INTERFACE UNIT6.1.1 Bus Signal DescriptionsTable 6-1 describes the signals associated with the BIU.Table 6-1. Bus Interface Unit Signals (Sheet

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-4M/IO#D/C#W/R#REFRESH#Device pins Bus Cycle Definition Signals (Memory/IO, Data/Control, Write/Rea

6-5BUS INTERFACE UNIT6.2 BUS OPERATIONThe processor generates eight different types of bus operations:• Memory data read (data fetch)• Memory data wri

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-6Figure 6-1. Basic External Bus Cycles StateA25:1, BHE#BLE#, D/C#M/IO#W/R#ADS#NA#D15:0RD#WR#BS8#

xiCONTENTS15.2.3 Refresh Addresses ...15-415.2.4 Bus Ar

6-7BUS INTERFACE UNIT6.2.1 Bus StatesThe processor uses a double-frequency clock input (CLK2). This clock is internally divided bytwo and synchronized

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-8Memory read and memory write cycles can be locked to prevent another bus master from usingthe loc

6-9BUS INTERFACE UNITNOTEPipelining is also supported during memory cycles initiated by the two integrated DMA units.Refer to “Pipelined Cycle” on pag

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-10• A doubleword (32-bit) transfer at (byte) address 03H requires three transfers, one word transf

6-11BUS INTERFACE UNITFigure 6-3. Ready Logic When an internal cycle occurs, the LBA# signal becomes active in Phase 1 of the first T2 state.It then s

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-12Figure 6-4 shows internal and external bus cycles.Figure 6-4. Basic Internal and External Bus Cy

6-13BUS INTERFACE UNIT6.3 BUS CYCLESThe processor executes five types of bus cycles:• Read• Write• Interrupt• Halt/shutdown• Refresh6.3.1 Read CycleRe

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-143. When a chip-select region is enabled for the current read cycle but internal READY# generatio

6-15BUS INTERFACE UNITFigure 6-5. Nonpipelined Address Read Cycles A2487-03LOCK#D15:0CLK2BHE#, BLE#, A25:1M/IO#, D/C#Valid1RD#READY#Ti T1 T2 T1 T2 T2

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-166.3.2 Write CycleWrite cycles are of two types: • Pipelined. Pipelined write cycles are describe

Intel386™ EX MICROPROCESSOR USER’S MANUALxiiCHAPTER 18JTAG TEST-LOGIC UNIT18.1 OVERVIEW ...

6-17BUS INTERFACE UNIT4. The WR# signal can be deasserted in two ways. • Early Ready: WR# is deasserted at the rising edge of CLK2 in the middle of th

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-18Figure 6-6. Nonpipelined Address Write Cycles A2488-02LOCK#D15:0CLK2BHE#, BLE#, A25:1M/IO#, D/C

6-19BUS INTERFACE UNIT6.3.3 Pipelined CycleThe pipelining feature of the processor is normally used to achieve zero-wait-state memory sub-systems usin

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-20Figure 6-7. Complete Bus States (Including Pipelined Address) A2376-02HOLD AssertedREADY# Assert

6-21BUS INTERFACE UNITFigure 6-8. Pipelined Address Cycles A2477-03LOCK#D15:0Valid 2Valid 3 Valid 4CLK2BHE#, BLE#, A25:1,M/IO#, D/C#Valid3Valid4Valid

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-22In cycle 3, NA# is sampled in the first T-state (T1P); the address and status have been valid fo

6-23BUS INTERFACE UNITA complete discussion of the considerations for using pipelining can be found in the Intel386™SX Processor datasheet (order numb

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-24NOTESince the CAS lines are invalid in the Ti states between the two interrupt acknowledge cycle

6-25BUS INTERFACE UNITFigure 6-9. Interrupt Acknowledge Cycles A2490-03CLK2BHE#BLE#, A25:A3, A1M/IO#, D/C#, W/R#LBA#LOCK#T2 T1 T2 Ti Ti Ti Ti T1 T2 T

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-266.3.5 Halt/Shutdown CycleThe halt condition occurs in response to a HALT instruction. The shutdo

xiiiCONTENTSAPPENDIX DSYSTEM REGISTER QUICK REFERENCED.1 PERIPHERAL REGISTER ADDRESSES...

6-27BUS INTERFACE UNITFigure 6-10. Halt Cycle A2492-02LOCK#D15:0CLK2BHE#, A1, M/IO#, W/R#RD#READY#T1 T2 T1 T2 Ti Ti Ti TiCycle 1Nonpipelined(Write)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-286.3.6 Refresh CycleThe refresh control unit simplifies dynamic memory controller design by issui

6-29BUS INTERFACE UNITFigure 6-11. Basic Refresh CycleA2491-02LOCK#D15:0CLK2BHE#, BLE#M/IO#, D/C#Valid 1RD#READY#Ti T1 T2 Ti T1 T2 T2 Ti Ti T1Cycle 1

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-30Figure 6-12. Refresh Cycle During HOLD/HLDA A2493-02D15:0HOLDCLK2BHE#, BLE#M/IO#, D/C#FloatingF

6-31BUS INTERFACE UNIT6.3.7 BS8 CycleThe BS8 cycle allows external logic to dynamically switch between an 8-bit data bus size and a16-bit data bus siz

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-32The BS8 cycle generates additional bus cycles for read and write cycles only. For interrupt andh

6-33BUS INTERFACE UNITFigure 6-13. 16-bit Cycles to 8-bit Devices (Using BS8#)StateA25:1M/IO#D/C#W/R#BHE#ADS#NA#D15:8RD#WR#BS8#READY#LOCK#Low ByteW

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-346.4 BUS LOCKIn a system in which more than one device (a bus master) may control the local bus,

6-35BUS INTERFACE UNITFigure 6-14. LOCK# Signal During Address Pipelining 6.4.3 LOCK# Signal DurationThe maximum duration of the LOCK# signal affects

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-366.5.1 HOLD/HLDA TimingTo gain control of the local bus, the requesting bus master drives the HOL

Intel386™ EX MICROPROCESSOR USER’S MANUALxivD.37 OCW1 (MASTER AND SLAVE)...

6-37BUS INTERFACE UNIT• NMI pin - The request is recognized and latched. It is serviced after HOLD is released.• SMI# pin - The request is recognized

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-386.6 DESIGN CONSIDERATIONS• Upon reset, UCS# is configured as a 16-bit chip-select signal. If the

6-39BUS INTERFACE UNIT6.6.1.1 System ConfigurationThe Intel387 SX Math Coprocessor can be interfaced to the Intel386 EX embedded processor asshown in

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-40The interface has these characteristics:• The Intel387 SX Math Coprocessor shares the local bus

6-41BUS INTERFACE UNITAlso, bit 5 in the PINCFG register (Figure 5-15 on page 5-24) must be cleared, to connect thecoprocessor-related signals of the

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-426.6.3 PSRAM InterfacePseudo SRAM (PSRAM) devices can be easily interfaced (Figure 6-17) to the I

6-43BUS INTERFACE UNIT6.6.4 Paged DRAM InterfaceExternal logic is required to interface the Intel386 EX processor to DRAM devices, as shown inFigure 6

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL6-446.6.5 Non-Paged DRAM InterfaceThis interface is similar to the Paged DRAM Interface, except that

7SYSTEM MANAGEMENT MODE

xvCONTENTSAPPENDIX EINSTRUCTION SET SUMMARYE.1 INSTRUCTION ENCODING AND CLOCK COUNT SUMMARY... E-1E.2 INSTRUCTION ENCO

7-1CHAPTER 7SYSTEM MANAGEMENT MODEThe Intel386™ EX processor provides a mechanism for system management with a combinationof hardware and CPU microcod

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-2• SMI# cannot interrupt currently executing SMM code. The processor latches the falling edge of a

7-3SYSTEM MANAGEMENT MODEports the relocation of SMRAM. When this bit is set (1), the processor supports SMRAM reloca-tion. When this bit is cleared (

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-4is no 64 Kbyte limit. The value loaded into the selector register is shifted to the left four bit

7-5SYSTEM MANAGEMENT MODEof the CPU is saved to the SMM State Dump Area. After executing a RSM instruction, the CPUproceeds to the next application co

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-6Figure 7-2. SMIACT# LatencyNOTEEven if bus cycles are pipelined, the minimum clock numbers are gu

7-7SYSTEM MANAGEMENT MODE7.3.2.1 SMI# PriorityWhen more than one exception or interrupt is pending at an instruction boundary, the processorservices t

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-87.3.2.2 System Management Interrupt During HALT CycleSince SMI# is an asynchronous signal, it may

7-9SYSTEM MANAGEMENT MODE7.3.2.3 HALT RestartIt is possible for SMI# to break into the HALT state. In some cases the application might want toreturn t

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-10Figure 7-5. SMI# Timing 7.3.2.5 I/O RestartBit 16 of the SMM Revision Identifier is set (1) indi

Intel386™ EX MICROPROCESSOR USER’S MANUALxviFIGURESFigure Page2-1 Intel386™ EX Embedded Processor Block Diagram ...

7-11SYSTEM MANAGEMENT MODEthen any pending INTR and NMI is serviced after completion of RSM instruction execution.Only one INTR and one NMI can be pen

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-12Figure 7-7. HALT During SMM Handler7.3.3.3 Idle Mode and Powerdown Mode During SMMBoth Idle Mode

7-13SYSTEM MANAGEMENT MODEexactly as if they represented another address line. The following options are supported by thechip select unit:To see how t

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-147.3.4.2 SMRAM State Dump AreaThe SMM State Save sequence asserts SMIACT#. This mechanism indicat

7-15SYSTEM MANAGEMENT MODEThe programmer should not modify the contents of this area in SMRAM space directly. SMRAMspace is reserved for CPU access on

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-167.5 PROGRAMMING CONSIDERATIONS7.5.1 System Management Mode Code ExampleThe following code exampl

7-17SYSTEM MANAGEMENT MODE---------------------------------------------------------------------------*/void SerialWriteStr2() /* Loops while writing a

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-18}/*************************** Function InitSIO *******************************Parameters:Unit Un

7-19SYSTEM MANAGEMENT MODE _SetEXRegByte(SIOPortBase + DLH, HIBYTE(BaudDivisor) ); _SetEXRegByte(SIOPortBase + DLL, LOBYTE(BaudDivisor) );// Set S

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL7-20 SetEXRegWordInline(CS2ADL,0x08700); // Enables SRAM as memory SetEXRegWordInline(CS2ADH,0x

xviiCONTENTSFIGURESFigure Page6-16 Intel386 EX Processor to SRAM/FLASH Interface...6-416-17 Intel386

8CLOCK AND POWER MANAGEMENT UNIT

8-1CHAPTER 8CLOCK AND POWER MANAGEMENT UNITThe clock generation circuitry provides uniform, nonoverlapping clock signals to the core and in-tegrated p

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL8-2Three of the internal peripherals have selectable clock sources.• The asynchronous serial I/O (SI

8-3CLOCK AND POWER MANAGEMENT UNITThe signal from the RESET pin is also routed to the clock generation unit, which synchronizesthe processor clock wit

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL8-4vice enters the programmed mode when the HALT cycle is terminated by a valid READY#. ThisREADY# m

8-5CLOCK AND POWER MANAGEMENT UNITFigure 8-3. SMM Interaction with Idle and Powerdown Modes8.1.2.2 Bus Interface Unit Operation During Idle ModeThe bu

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL8-68.1.3 Clock and Power Management Registers and Signals Table 8-1 lists the registers and Table 8-

8-7CLOCK AND POWER MANAGEMENT UNIT8.2 CONTROLLING THE PSCLK FREQUENCYThe PSCLK signal can provide a 50% duty cycle prescaled clock to the timer/counte

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL8-88.3 CONTROLLING POWER MANAGEMENT MODESTwo power management modes are available: idle and powerdow

Intel386™ EX MICROPROCESSOR USER’S MANUALxviiiFIGURESFigure Page10-7 Mode 1 – Writing a New Count...

8-9CLOCK AND POWER MANAGEMENT UNIT8.3.1 Idle ModeIdle mode freezes the core clocks (PH1C low and PH2C) high, and leaves the peripheral clocks(PH1P and

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL8-108.3.2 Powerdown ModePowerdown mode freezes both the core clocks and the peripheral clocks (PH1C

8-11CLOCK AND POWER MANAGEMENT UNITFigure 8-7. Timing Diagram, Entering and Leaving Powerdown Mode8.4 DESIGN CONSIDERATIONSThis section outlines desig

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL8-12Figure 8-8. Reset Synchronization Circuit8.4.2 Power-up Considerations8.4.2.1 Built-in Self Test

8-13CLOCK AND POWER MANAGEMENT UNIT8.4.3 Powerdown Mode and Idle Mode Considerations• The “wake-up” signals (INT, NMI, and SMI#) are level-sensitive i

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL8-14NoneSyntax: int error; WORD psclk = 0x02; error = Set_Prescale_Value(psclk); Real

8-15CLOCK AND POWER MANAGEMENT UNIT No changes required.******************************************************************************/ void Ente

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL8-16 /* clear lowest two bits of pwrcon */ pwrcon = pwrcon & 0xfc; /* Set mode to powerdo

9INTERRUPT CONTROL UNIT

Intel386 EXEmbeddedMicroprocessorUser’s Manual1996™

xixCONTENTSFIGURESFigure Page11-21 Modem Control Register (MCRn)...11-3011-2

9-1CHAPTER 9INTERRUPT CONTROL UNITThe Interrupt Control Unit (ICU) consists of two cascaded interrupt controllers, a master and aslave, that allow int

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-2The slave 82C59A is cascaded from (or connected to) the master’s IR2 signal. Like the master,the

9-3INTERRUPT CONTROL UNITFigure 9-1. Interrupt Control Unit ConfigurationIR0IR1IR28259AMasterIR401INT0(P3.2)†To/From I/O Port 3P3CFG.2VSSP3CFG.2IR5I

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-49.2 ICU OPERATIONThe following sections describe the ICU operation. The ICU’s interrupt sources,

9-5INTERRUPT CONTROL UNITTable 9-1. 82C59A Master and Slave Interrupt Sources Master IR LineSourceConnectedbySlaveIR LineSourceConnectedbyIR0 TMROUT0(

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-6Interrupt processing begins with the assertion of an IR signal. During the ICU initialization pro

9-7INTERRUPT CONTROL UNITFigure 9-2. Methods for Changing the Default Interrupt Structure9.2.2.2 Determining PriorityThere are three modes that determ

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-8processing of a lower-level slave interrupt. The special fully nested mode is generally used by t

9-9INTERRUPT CONTROL UNIT9.2.4 Interrupt ProcessEach IR signal has a mask, a pending, and an in-service bit associated with it. • The mask bit disable

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-10NOTEUnlike the AEOI mode (this is a mode, and not a command like specific EOI or nonspecific EOI

Intel386™ EX MICROPROCESSOR USER’S MANUALxxFIGURESFigure Page13-7 SSIO Transmitter with Autotransmit Mode Disabled ...

9-11INTERRUPT CONTROL UNITFigure 9-3. Interrupt Process – Master Request from Non-slave SourceA2427-01Master receives an interrupt request. (From a no

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-12Figure 9-4. Interrupt Process – Slave RequestSlave receives an interrupt request.Slave sets the

9-13INTERRUPT CONTROL UNITFigure 9-5. Interrupt Process – Master Request from Slave SourceA2429-02Master receives IR2 interrupt request.Master sets it

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-14The interrupt’s priority structure determines which EOI command should be used. Use the spe-cifi

9-15INTERRUPT CONTROL UNITconfiguring more than six external 82C59As. Since the polling mode doesn’t require that the ad-ditional 82C59As be cascaded

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-16Table 9-2. ICU Registers (Sheet 1 of 2)RegisterExpandedAddressPC/AT* AddressFunctionP3CFG(read/w

9-17INTERRUPT CONTROL UNITTo initialize the 82C59As: 1. Globally disable all maskable interrupts to the core using the CLI instruction.2. Write to the

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-189.3.1 Port 3 Configuration Register (P3CFG)Use the P3CFG register to connect the interrupt reque

9-19INTERRUPT CONTROL UNIT9.3.2 Interrupt Configuration Register (INTCFG)Use the INTCFG register to connect the INT9:4 interrupt request pins to the m

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-209.3.3 Initialization Command Word 1 (ICW1)Initialization begins with writing ICW1. Use ICW1 to s

xxiCONTENTSFIGURESFigure Page17-4 WDT Reload Value Registers (WDTRLDH and WDTRLDL)...17-1017-5 Power Control Register

9-21INTERRUPT CONTROL UNIT9.3.4 Initialization Command Word 2 (ICW2)Use the ICW2 register to define the base interrupt vector for the 82C59A. Valid ve

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-229.3.5 Initialization Command Word 3 (ICW3)The ICW3 register contains information about the maste

9-23INTERRUPT CONTROL UNITICW3 (at 0F0A1H or 00A1H) is the internal slave ID register (Figure 9-11). Use this register toindicate that the slave is ca

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-249.3.6 Initialization Command Word 4 (ICW4)Use ICW4 to select the special-fully nested mode or th

9-25INTERRUPT CONTROL UNIT9.3.7 Operation Command Word 1 (OCW1)OCW1 is the interrupt mask register. Setting a bit in the interrupt mask register disab

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-269.3.8 Operation Command Word 2 (OCW2)Use OCW2 to change the priority structure and issue EOI com

9-27INTERRUPT CONTROL UNIT9.3.9 Operation Command Word 3 (OCW3)Use OCW3 to enable the special mask mode, issue a poll command, and provide access to t

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-289.3.10 Interrupt Request Register (IRR)This 8-bit, read-only register contains the levels reques

9-29INTERRUPT CONTROL UNIT9.4 DESIGN CONSIDERATIONSThe following sections discuss some design considerations.9.4.1 Interrupt Acknowledge CycleWhen the

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-30Level triggered The 82C59A recognizes a high level on an IR line as an interruptrequest. A devic

Intel386™ EX MICROPROCESSOR USER’S MANUALxxiiTABLESTable Page2-1 PC-compatible Peripherals...

9-31INTERRUPT CONTROL UNITFigure 9-19. Cascading External 82C59A Interrupt ControllersA2857-01READY#W/R#D/C#ADS#CLKOUTCLK2INTA#andREADY#StateMachi

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-329.5 PROGRAMMING CONSIDERATIONSConsider the following when programming the ICU.• When an 82C59A r

9-33INTERRUPT CONTROL UNITBYTE _CascadeBits_ = 0x4;/*****************************************************************************InitICUDescriptio

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-34Real/Protected ModeNo changes required.*********************************************************

9-35INTERRUPT CONTROL UNIT/*****************************************************************************InitICUSlaveDescription:Initialization only th

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-36 _IRQ_SlaveBase_ = SlaveBase & 0xf8; _SetEXRegByte(ICW1S, 0x11 | SlaveMode); // Set slave

9-37INTERRUPT CONTROL UNIT#define IR7 0x80 Disable8259Interrupt(IR0 | IR1 | IR3 | IR4 | IR5 | IR6 | IR7, IR1 | IR2 | IR3 | IR4 |IR5 | IR6);Real/P

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-38/* ICU IRQ Mask Values*/#define IR0 0x1#define IR1 0x2#define IR2 0x4#define IR3 0x8#define IR4

9-39INTERRUPT CONTROL UNITsupports INTERRUPT_ISR (parameter is ignored). Protected mode supports both.Returns:Error CodeE_INVALID_VECTOR -- An IRQ

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL9-40return E_OK; }/* SetIRQVector */

xxiiiCONTENTSTABLESTable Page13-2 Maximum and Minimum Baud-rate Output Frequencies...13-613-3 SSIO Registers.

9-41INTERRUPT CONTROL UNITPoll_Command:Description:This routine issues a poll command which reads the poll status byteof the ICU.Parameters:Master_or_

10TIMER/COUNTER UNIT

10-1CHAPTER 10TIMER/COUNTER UNITThe Timer/counter Unit (TCU) has the same basic functionality as the industry-standard 82C54counter/timer. It contains

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-2Therefore, the OUTn signals can drive external devices, generate interrupt requests, initiate DMA tra

10-3TIMER/COUNTER UNIT10.1.1 TCU Signals and RegistersTable 10-1 and Table 10-2 lists the signals and registers associated with the TCU.Table 10-1. TC

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-4Table 10-2. TCU Associated Registers RegisterExpandedAddressPC/AT* AddressFunctionP3CFGPINCFG(read/wr

10-5TIMER/COUNTER UNIT10.2 TCU OPERATIONEach counter can operate in any one of six operating modes. These modes are described in sec-tions 10.2.1 thro

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-610.2.1 Mode 0 – Interrupt on Terminal CountThis mode allows you to generate a rising edge on a counte

10-7TIMER/COUNTER UNITFigure 10-2. Mode 0 – Basic OperationFigure 10-3 shows suspending the counting sequence. A low level on GATEn causes the counter

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-8Figure 10-4 shows writing a new count before the current count reaches zero. The counter loadsthe new

10-9TIMER/COUNTER UNITFigure 10-5. Mode 1 – Basic OperationFigure 10-6 shows retriggering the one-shot. On the CLKINn pulse following the retrigger, t

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-10Figure 10-7 shows writing a new count. The counter waits for a gate-trigger to load the new count.Th

10-11TIMER/COUNTER UNITFigure 10-8. Mode 2 – Basic OperationFigure 10-9 shows suspending the counting sequence. A low level on GATEn causes the counte

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-12Figure 10-10 shows writing a new count. The counter loads the new count after the counter reach-es o

10-13TIMER/COUNTER UNITFigure 10-11. Mode 3 – Basic Operation (Even Count)Odd count basic operation:1. After a control word write, OUTn is driven high

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-14Figure 10-12. Mode 3 – Basic Operation (Odd Count)NOTEFor an even count of N, OUTn remains high for

10-15TIMER/COUNTER UNITFigure 10-14 and Figure 10-15 shows writing a new count. If the counter receives a gate-triggerafter writing a new count but be

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-1610.2.5 Mode 4 – Software-triggered StrobeInitializing a counter for mode 4 drives the counter’s OUTn

1GUIDE TO THIS MANUAL

10-17TIMER/COUNTER UNITFigure 10-17 shows suspending the counting sequence. A low level on GATEn causes the counterto suspend counting (both the state

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-1810.2.6 Mode 5 – Hardware-triggered StrobeInitializing a counter for mode 5 sets the counter’s OUTn s

10-19TIMER/COUNTER UNITFigure 10-20 shows retriggering the strobe with a gate-trigger. On the CLKINn pulse followingthe retrigger, the counter reloads

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-2010.3 REGISTER DEFINITIONSThe following sections describe how to configure a counter’s input and outp

10-21TIMER/COUNTER UNIT.Figure 10-22. Timer Configuration Register (TMRCFG)Timer ConfigurationTMRCFG(read/write)Expanded Addr:ISA Addr:Reset State:F83

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-22The peripheral pin selection registers (P3CFG and PINCFG) determine whether each counter’sOUTn signa

10-23TIMER/COUNTER UNITUse PINCFG bit 5 to connect TMROUT2, TMRCLK2, and TMRGATE2 to package pins.Figure 10-24. Pin Configuration Register (PINCFG)Pin

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-2410.3.2 Initializing the CountersThe timer control register (TMRCON) has three formats: control word,

10-25TIMER/COUNTER UNITFigure 10-25. Timer Control Register (TMRCON – Control Word Format)Timer Control (Control Word Format)TMRCONExpanded Addr:ISA A

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-2610.3.3 Writing the CountersUse the write format of a counter’s Timer n register (TMRn) to specify a

10-27TIMER/COUNTER UNIT10.3.4 Reading the CounterTo read the counter you can perform a simple read operation or send a latch command to thecounter. TM

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-28Figure 10-27. Timer Control Register (TMRCON – Counter-latch Format)When a counter receives a counte

10-29TIMER/COUNTER UNITYou can interleave reads and writes of the same counter; for example, if the counter is pro-grammed for the two-byte read/write

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-3010.3.4.3 Read-back CommandUse the read-back format of TMRCON (Figure 10-29) to latch the count and/o

10-31TIMER/COUNTER UNITThe read-back command can latch the count and status of multiple counters. This single com-mand is functionally equivalent to s

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-32Figure 10-30. Timer n Register (TMRn – Status Format)Timer n (Status Format)TMRn (n = 0–2)Expanded A

10-33TIMER/COUNTER UNITWhen a counter receives multiple read-back commands, it ignores all but the first command; thecount/status that the core reads

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-34• With the readback command:— If both the status and counter values are latched, the user can read t

10-35TIMER/COUNTER UNITReturns:Error Codes E_INVALID_DEVICE -- Unit number specifies a non-existing

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-36 if(!Enable) TmpByte |= 0x80; // Set Timer Disable Bit TmpByte |= (Inputs << (Unit*

1-1CHAPTER 1GUIDE TO THIS MANUALThis manual describes the Intel386™ EX Embedded Processor. It is intended for use by hardwaredesigners familiar with t

10-37TIMER/COUNTER UNIT#define DISABLE 0 SetUp_ReadBack(DISABLE, DISABLE, ENABLE, ENABLE, ENABLE); Real/Protected Mode: No changes required **

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-38Returns: Counter Value of specified timer

10-39TIMER/COUNTER UNIT/*****************************************************************************

Intel386™ EX EMBEDDED PROCESSOR USER’S MANUAL10-40 case TMR_2: CountL = _GetEXRegByte(TMR2); CountH = _GetEXRegByte(TMR2); break; } Coun

10-41TIMER/COUNTER UNIT/*****************************************************************************Example of how to write a new initial counter val

11ASYNCHRONOUS SERIAL I/O UNIT

11-1CHAPTER 11ASYNCHRONOUS SERIAL I/O UNITThe asynchronous serial I/O (SIO) unit provides a means for the system to communicate with ex-ternal periphe

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-2Figure 11-1. Serial I/O Unit 1 ConfigurationA2519-02BCLKINReceive DataTransmit DataRequest to Se

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL1-2Chapter 9 — Interrupt Control Unit — describes the interrupt sources and priority options andexpl

11-3ASYNCHRONOUS SERIAL I/O UNIT11.1.1 SIO SignalsTable 11-1 lists the SIOn signals.Table 11-1. SIO SignalsSignalDevice Pin or Internal SignalDescript

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-411.2 SIO OPERATIONThe following sections describe the operation of the baud-rate generator, tran

11-5ASYNCHRONOUS SERIAL I/O UNITThe baud-rate generator’s output frequency is determined by BCLKIN and a divisor as follows.,The minimum divisor value

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-611.2.2 SIOn TransmitterThe data frame for transmissions is programmable. It consists of a start

11-7ASYNCHRONOUS SERIAL I/O UNITFigure 11-3. SIOn TransmitterThe transmitter contains a transmitter empty (TE) flag and a transmit buffer empty (TBE)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-8Figure 11-4. SIOn Data Transmission Process Flow A2527-02 Select the BCLKIN source andthe t

11-9ASYNCHRONOUS SERIAL I/O UNIT11.2.3 SIOn ReceiverThe data frame for receptions is programmable, and is identical to the data frame for transmis-sio

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-10The receiver contains a receive buffer full (RBF) flag and flags for each of the error conditio

11-11ASYNCHRONOUS SERIAL I/O UNITFigure 11-6. SIOn Data Reception Process FlowA2525-02Select the BCLKIN source andthe receiver input baud rate.Selec

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-1211.2.4 Modem ControlThe modem control logic provides interfacing for four input signals and two

Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including in-fringement of any pate

1-3GUIDE TO THIS MANUAL1.2 NOTATIONAL CONVENTIONSThe following notations are used throughout this manual. # The pound symbol (#) appended to a signal

11-13ASYNCHRONOUS SERIAL I/O UNIT11.2.6 SIO Interrupt and DMA Sources11.2.6.1 SIO Interrupt SourcesEach SIO channel has four status signals: receiver

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-1411.2.7 External UART SupportMany PC compatible applications may need to support COM3 and COM4 s

11-15ASYNCHRONOUS SERIAL I/O UNIT11.3 REGISTER DEFINITIONSTable 11-5 lists the registers associated with the SIO unit and the following sections conta

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-16For PC compatibility, the SIO unit accesses its 11 registers through 8 I/O addresses. The RBRn,

11-17ASYNCHRONOUS SERIAL I/O UNIT11.3.1 Pin and Port Configuration Registers (PINCFG and PnCFG [n = 1–3])Use PINCFG bits 2:0 to connect the SIO1 signa

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-18Use P1CFG bits 4:0 to connect SIO0 signals to package pins.Figure 11-8. Port 1 Configuration Re

11-19ASYNCHRONOUS SERIAL I/O UNITUse P2CFG bits 7–5 to connect SIO0 signals to package pins.Figure 11-9. Port 2 Configuration Register (P2CFG)Port 2 C

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-20Use P3CFG bit 7 to connect the COMCLK pin to the package pin.Figure 11-10. Port 3 Configuration

11-21ASYNCHRONOUS SERIAL I/O UNIT11.3.2 SIO and SSIO Configuration Register (SIOCFG)Use SIOCFG to select the baud-rate generator clock source for the

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-2211.3.3 Divisor Latch Registers (DLLn and DLHn)Use these registers to program the baud-rate gene

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL1-4Register Bits When the text refers to more that one bit, the range may appear as twonumbers separ

11-23ASYNCHRONOUS SERIAL I/O UNIT11.3.4 Transmit Buffer Register (TBRn)Write the data words to be transmitted to TBRn. Use the interrupt control or DM

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-2411.3.5 Receive Buffer Register (RBRn)Read RBRn to obtain the last data word received. Use the i

11-25ASYNCHRONOUS SERIAL I/O UNIT11.3.6 Serial Line Control Register (LCRn)Use LCRn to provide access to the multiplexed registers, send a break condi

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-2611.3.7 Serial Line Status Register (LSRn)Use LSRn to check the status of the transmitter and re

11-27ASYNCHRONOUS SERIAL I/O UNIT11.3.8 Interrupt Enable Register (IERn)Use IERn to connect the SIOn status signals to the interrupt control unit. All

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-2811.3.9 Interrupt ID Register (IIRn)Use the IIRn to determine whether an interrupt is pending an

11-29ASYNCHRONOUS SERIAL I/O UNIT11.3.10 Modem Control Register (MCRn)Use MCRn to put the SIOn into a diagnostic test mode. In this mode, the modem in

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-30Figure 11-21. Modem Control Register (MCRn)Modem ControlMCR0, MCR1(read/write)Expanded Addr:ISA

11-31ASYNCHRONOUS SERIAL I/O UNIT11.3.11 Modem Status Register (MSRn)Read MSRn to determine the status of the modem control input signals. The upper f

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-3211.3.12 Scratch Pad Register (SCRn)SCRn is available for use as a scratch pad. Writing and read

1-5GUIDE TO THIS MANUALReserved Bits Reserved bits are not used in this device, but they may be used in future implementations. Follow these guideline

11-33ASYNCHRONOUS SERIAL I/O UNIT11.4.1 Asynchronous Serial I/O Unit Code ExamplesThe code example contains these software routines:InitSIO Initialize

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-34optionsModemCntrl Defines the operation of the modem control lines BaudRate Specifies baud rate

11-35ASYNCHRONOUS SERIAL I/O UNITreturn E_INVALID_DEVICE;/* Set Port base based on serial port used */SIOPortBase = (Unit ? SIO1_BASE : SIO0_BASE);/*

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-36#define SIO_0 0#define LENGTH 32 char String_Read[LENGTH];int error;error = SerialReadSt

11-37ASYNCHRONOUS SERIAL I/O UNITuntil a character has been received from the serial port.Parameters:Unit Unit number of the serial port. 0 for SIO po

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-38SerialWriteChar:Description:Is a Polled serial port write function that waits forever or until

11-39ASYNCHRONOUS SERIAL I/O UNITDescription:Is a Polled serial port write function that waits forever or until all characters have been written to th

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-40/*****************************************************************************SerialWriteMem:De

11-41ASYNCHRONOUS SERIAL I/O UNIT}} /* SerialWriteMem */

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-42 if ((msr0 & 0x04) && (msr0 & 0x40)) { /* ring indicator */ } i

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL1-61.5 ELECTRONIC SUPPORT SYSTEMSIntel’s FaxBack* service and application BBS provide up-to-date tec

11-43ASYNCHRONOUS SERIAL I/O UNIT /********************************************************

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL11-44Description:Is an interrupt driven serial port write function.The NUL character (‘\0’) is used

11-45ASYNCHRONOUS SERIAL I/O UNITNoneAssumptions:NoneSyntax:Not called by user.Real/Protected Mode:No changes required.

12DMA CONTROLLER

12-1CHAPTER 12DMA CONTROLLERThe DMA controller improves system performance by allowing external or internal peripheralsto directly transfer informatio

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-2Figure 12-1. DMA Unit Block DiagramA2531-02DREQ0DMAACK0#DREQ1DMAACK1#DMAINTDMABus ArbiterHOLDHLD

12-3DMA CONTROLLER12.1.1 DMA TerminologyThis section provides a definition of some of the terms used in this chapter to describe the DMAcontroller.DMA

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-412.1.2 DMA SignalsTable 12-1 describes the DMA signals.Table 12-1. DMA SignalsSignalDevice Pin o

1-7GUIDE TO THIS MANUAL7. Microprocessor, PCI, and peripheral catalog8. Quality and reliability and change notification catalog9. iAL (Intel Architect

12-5DMA CONTROLLER12.2 DMA OPERATIONThe following sections describe the operation of the DMA. See “Register Definitions” on page12-28 for details on i

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-6data bus, depending on the transfer direction. Since the requester is selected via the DACKn# si

12-7DMA CONTROLLERDMACFG register), but the Requester address registers would be programmed with one of thememory addresses. It doesn’t really matter

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-8Figures 12-2 and 12-3 are simple diagrams of how the Temporary Register is filled and emptiedfor

12-9DMA CONTROLLER12.2.3 Starting DMA TransfersInternal I/O, external I/O, or memory can request DMA service. The internal I/O requesters (theasynchro

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-10control request, the bus arbiter services these requests by issuing an internal hold signal req

12-11DMA CONTROLLERTerminating a buffer transfer by deasserting DREQn can also be done either synchronously orasynchronously. The effect is identical

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-1212.2.6 Buffer-transfer ModesAfter a buffer transfer is completed or terminated, a channel can e

12-13DMA CONTROLLERThe DMAINT signal is active immediately after the Chaining Process has been entered, as thechannel then perceives the Base Register

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-14transfer is suspended and the channel waits for the request input to be reactivated before it c

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL1-81.7 PRODUCT LITERATUREYou can order product literature from the following Intel literature center

12-15DMA CONTROLLERFigure 12-8. Single Data-transfer Mode with Single Buffer-transfer ModeA2331-02After initialization, the DMA channel isprogrammed

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-16Figure 12-9. Single Data-transfer Mode with Autoinitialize Buffer-transfer ModeA2332-02YesNoDR

12-17DMA CONTROLLERFigure 12-10. Single Data-transfer Mode with Chaining Buffer-transfer ModeIs therea new processto set up?No new transfer inform

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-1812.2.7.2 Block Data-transfer ModeIn block data-transfer mode, a channel request initiates a buf

12-19DMA CONTROLLERFigure 12-11. Block Data-transfer Mode with Single Buffer-transfer ModeA2334-02Buffer transfer is complete, so channelbecomes idle

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-20Figure 12-12. Block Data-transfer Mode with Autoinitialize Buffer-transfer ModeA2333-02YesNoDRE

12-21DMA CONTROLLER12.2.7.3 Demand Data-transfer ModeIn demand data-transfer mode, a channel request initiates a buffer transfer. The channel gains bu

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-22Figure 12-14. Demand Data-transfer Mode with Single Buffer-transfer ModeAfter initialization, t

12-23DMA CONTROLLERFigure 12-15. Demand Data-transfer Mode with Autoinitialize Buffer-transfer ModeAfter initialization, the DMA channel isprogrammed

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-24Figure 12-16. Demand Data-transfer Mode with Chaining Buffer-transfer ModeNo new transfer info

2ARCHITECTURAL OVERVIEW

12-25DMA CONTROLLER12.2.8 Cascade ModeCascade mode allows an external 8237A or another DMA-type device to gain bus control. A cas-caded device request

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-26Figure 12-17. Cascade Mode12.2.9 DMA InterruptsEach channel contains two interrupt causing sign

12-27DMA CONTROLLERThe four interrupt source signals (two per channel) are internally connected (ORed) to the inter-rupt request output (DMAINT). When

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-2812.3 REGISTER DEFINITIONSTable 12-3 lists the registers associated with the DMA unit, and the f

12-29DMA CONTROLLERDMASTS(read only)F008H 0008H DMA Status:Indicates whether a hardware request is pending on channel 0 and 1. Indicates whether chann

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-30DMACHR(write only)F019H — DMA Chaining:Enables chaining buffer-transfer mode for a specified ch

12-31DMA CONTROLLER12.3.1 Pin Configuration Register (PINCFG)Use PINCFG to connect DACK0#, EOP#, and DACK1# to package pins.Figure 12-18. Pin Configur

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-3212.3.2 DMA Configuration Register (DMACFG)Use DMACFG to select one of the hardware sources for

12-33DMA CONTROLLER12.3.3 Channel RegistersTo program a DMA channel’s requester and target addresses and its byte count, write to the DMAchannel regis

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-34NOTEThe value you write to the byte count register must be one less than the number of bytes to

12-35DMA CONTROLLER12.3.5 Command 1 Register (DMACMD1)Use DMACMD1 to enable both channels and to select the rotating method for changing the buscontro

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-3612.3.6 Status Register (DMASTS)Use DMASTS to check the status of the channels individually. The

12-37DMA CONTROLLER12.3.7 Command 2 Register (DMACMD2)Use DMACMD2 to select the DREQn and EOP# sampling: asynchronous or synchronous. Bustiming diagra

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-3812.3.8 Mode 1 Register (DMAMOD1)Use DMAMOD1 to select a particular channel’s data-transfer mode

12-39DMA CONTROLLERFigure 12-25. DMA Mode 1 Register (DMAMOD1)DMA Mode 1DMAMOD1(write only)Expanded Addr:ISA Addr:Reset State:F00BH000BH00H7 0DTM1 DTM

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-4012.3.9 Mode 2 Register (DMAMOD2)Use DMAMOD2 to select the data transfer bus cycle option, speci

12-41DMA CONTROLLERFigure 12-26. DMA Mode 2 Register (DMAMOD2)DMA Mode 2DMAMOD2(write only)Expanded Addr:ISA Addr:Reset State:F01BH—00H7 0BCO RD TD RH

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-4212.3.10 Software Request Register (DMASRR)Write DMASRR to issue software DMA service requests.

12-43DMA CONTROLLERRead DMASRR to see whether a software request for a particular channel is pending. Each re-quest bit is cleared upon Terminal Count

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-4412.3.11 Channel Mask and Group Mask Registers (DMAMSK and DMAGRPMSK)Use the DMAMSK and DMAGRPMS

2-1CHAPTER 2ARCHITECTURAL OVERVIEWThe Intel386™ EX embedded processor (Figure 2-1) is based on the static Intel386 SX processor.This highly integrated

12-45DMA CONTROLLERFigure 12-30. DMA Group Channel Mask Register (DMAGRPMSK)DMA Group Channel MaskDMAGRPMSK(read/write)Expanded Addr:ISA Addr:Reset St

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-4612.3.12 Bus Size Register (DMABSR)Use DMABSR to determine the requester and target data bus wid

12-47DMA CONTROLLER12.3.13 Chaining Register (DMACHR)Use DMACHR to enable or disable the chaining buffer-transfer mode for a selected channel. Thefoll

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-4812.3.14 Interrupt Enable Register (DMAIEN)Use DMAIEN to individually connect channel 0’s and 1’

12-49DMA CONTROLLER12.3.15 Interrupt Status Register (DMAIS)DMAIS indicates which source activated the DMA interrupt request signal (channel 0 transfe

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-5012.3.16 Software CommandsThe DMA contains four software commands: clear byte pointer, clear DMA

12-51DMA CONTROLLERwith BP=0 causes the DMA to set BP. The clear byte pointer software command (DMACLRBP) allows you to force BP to a known state (0)

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-52InitDMA1ForSSIXmitterToMem Initializes DMA channel1 for transfers between the SIO transmitter p

12-53DMA CONTROLLER /* given channel*/}/**********************************************************************

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-54 Description: Sets the requester to an I/O port address, wIO, for the DMA channel s

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL2-2Figure 2-1. Intel386™ EX Embedded Processor Block DiagramA2849-02JTAG UnitClock and PowerManagem

12-55DMA CONTROLLER Description: Sets the target memory address for the DMA channel specified by nChannel. Parameters: nChannel -

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-56 #else /*Else in compact, large, or huge memory model*/ wSegment = _FP_SEG(ptMemory

12-57DMA CONTROLLER*****************************************************************************/int SetDMAXferCount(int nChannel, DWORD lCount){ WO

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-58 Syntax: InitDMA(); //Initialize DMA peripheral Real/Protected Mode: No chang

12-59DMA CONTROLLER . SetDMATargMemAddr(DMA_Channel1, lpsz); //Set target memory address //Set t

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL12-60 _SetEXRegByte(DMABSR, 0x51); /*DMABSR[7]=0: reserved*/ /*DMAB

12-61DMA CONTROLLER None Syntax: regDMAIE = _GetEXRegByte(DMAIEN) | 0x2; //Enable tc interrupt for // channel 0 _SetEXRegByte(

13SYNCHRONOUS SERIAL I/O UNIT

iiiCONTENTSCHAPTER 1GUIDE TO THIS MANUAL1.1 MANUAL CONTENTS...

2-3ARCHITECTURAL OVERVIEW2.2 INTEGRATED PERIPHERALSThe Intel386 EX processor integrates both PC-compatible peripherals (Table 2-1) and peripheralsthat

13-1CHAPTER 13SYNCHRONOUS SERIAL I/O UNITThe synchronous serial I/O (SSIO) unit provides 16-bit bidirectional serial communications. Thetransmit and r

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-2Figure 13-1. Transmitter and Receiver in Master ModeFigure 13-2. Transmitter in Master Mode, Rec

13-3SYNCHRONOUS SERIAL I/O UNITFigure 13-3. Transmitter in Slave Mode, Receiver in Master ModeFigure 13-4. Transmitter and Receiver in Slave ModeRecei

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-413.1.1 SSIO SignalsTable 13-1 lists the SSIO signals.Table 13-1. SSIO SignalsSignalDevice Pin or

13-5SYNCHRONOUS SERIAL I/O UNIT13.2 SSIO OPERATIONThe following sections describe the operation of the baud-rate generator, transmitter, and receiv-er

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-6The baud-rate generator contains a seven-bit down counter. A programmable baud-rate value(BV) is

13-7SYNCHRONOUS SERIAL I/O UNIT13.2.2.1 Transmit Mode using Enable BitThe transmitter contains a transmit holding buffer empty (THBE) flag and a trans

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-8Figure 13-7. SSIO Transmitter with Autotransmit Mode DisabledThe SSIO Unit can be operated eithe

13-9SYNCHRONOUS SERIAL I/O UNITFigure 13-8. Transmit Data by PollingA3394-01NoTUE=1?YesErrorRoutineAUTOTXM=1?NoYesAUTOTXM=1?Enable TransmitterTEN

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-10Figure 13-9. Interrupt Service Routine for Transmitting Data Using InterruptsA3398-01THBE=1?Er

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL2-4Table 2-2. Embedded Application-specific Peripherals Name DescriptionSystem Management Mode (SMM)

13-11SYNCHRONOUS SERIAL I/O UNITIf the transmitter is disabled while a data value in the shift register is being shifted out, it continuesrunning unti

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-1213.2.2.2 Autotransmit ModeSet the AUTOTXM bit (SSIOCON2.2) and the TXMM bit (SSIOCON2.1) to ena

13-13SYNCHRONOUS SERIAL I/O UNITThe SSIO Unit can be operated either by using a polling method or through interrupts. • Figure 13-12 shows a basic flo

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-14Figure 13-13. Interrupt Service Routine for Receiving Data Using InterruptsA3397-01ROE=0?Error

13-15SYNCHRONOUS SERIAL I/O UNITIf the receiver is disabled while a data value is being shifted into the shift register, it continuesrunning until the

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-1613.3 REGISTER DEFINITIONSTable 13-3 list the registers associated with the SSIO and the followi

13-17SYNCHRONOUS SERIAL I/O UNIT13.3.1 Pin Configuration Register (PINCFG)The serial receive clock (SRXCLK) and transmit serial data (SSIOTX) pins are

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-1813.3.2 SIO and SSIO Configuration Register (SIOCFG)Use SIOCFG bit 2 to connect either PSCLK or

13-19SYNCHRONOUS SERIAL I/O UNIT13.3.3 Prescale Clock Register (CLKPRS)Use CLKPRS to program the PSCLK frequency. Figure 13-17. Clock Prescale Registe

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-2013.3.4 SSIO Baud-rate Control Register (SSIOBAUD)Use SSIOBAUD to enable the baud-rate generator

3CORE OVERVIEW

13-21SYNCHRONOUS SERIAL I/O UNIT13.3.5 SSIO Baud-rate Count Down Register (SSIOCTR)Read SSIOCTR to determine the status of the baud-rate generator. Th

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-22Figure 13-20. SSIO Control 1 Register (SSIOCON1)SSIO Control 1SSIOCON1(read/write)Expanded Addr

13-23SYNCHRONOUS SERIAL I/O UNIT13.3.7 SSIO Control 2 Register (SSIOCON2)Use the control bits TXMM and RXMM in SSIOCON2 to put the transmitter or rece

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-2413.3.8 SSIO Transmit Holding Buffer (SSIOTBUF)Write the data words to be transmitted to SSIOTBU

13-25SYNCHRONOUS SERIAL I/O UNIT13.3.9 SSIO Receive Holding Buffer (SSIORBUF)Read SSIORBUF to obtain the last data word received. Use the interrupt co

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-2613.5 PROGRAMMING CONSIDERATIONS• When operating the transmitter in Master mode, and not in Auto

13-27SYNCHRONOUS SERIAL I/O UNIT Initialization routine for Synchronous Serial I/O Port. Parameters: Mode Enables receiver and transmitter; Enab

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-28/* Init Baud Rate Generator */ _SetEXRegByte(SSIOBAUD,BaudValue);}_SetEXRegByte(SSIOCON1,Mod

13-29SYNCHRONOUS SERIAL I/O UNIT/* Disable Receiver */_SetEXRegByte(SSIOCON1, SSControl);}else { // Slave Receiver, Receiver MUST already be Enabled /

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-30 /* Get Control Register Ready to disable */SSControl &= (~SSIO_TX_ENAB); // Clear the bi

13-31SYNCHRONOUS SERIAL I/O UNIT Slave to clear the in-service bit. It is also assumed that the Master is not operating in AEOI, SFNM, or SMM.

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL13-32NoneSyntax: Not called by userReal/Protected Mode: No changes required. **********************

13-33SYNCHRONOUS SERIAL I/O UNIT _SetEXRegWord(SSIOTBUF, value); value++; } else { /* Disable Transmitter and Transmitter interrupts */

14CHIP-SELECT UNIT

14-1CHAPTER 14CHIP-SELECT UNITThe Chip-select Unit (CSU) of the processor can be used to eliminate external address and bus-cycle decoders in your sys

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-214.2 CSU UPON RESETUpon reset of the processor, only the UCS channel is enabled and all other ch

14-3CHIP-SELECT UNITFigure 14-1. Channel Address Comparison LogicThe lower address bits are excluded from address comparisons (only 15 bits are compar

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-4Figure 14-2. Determining a Channel’s Address Block SizeAny ones that are to the left of the righ

3-1CHAPTER 3CORE OVERVIEWThe Intel386™ EX processor core is based upon the Intel386 CX processor, which is an enhancedversion of the Intel386 SX proce

14-5CHIP-SELECT UNITExample 1This example establishes a single 32-Kbyte address block starting at 1340000H (a 32-Kbyteboundary). In this example, the

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-6Example 2This example establishes four 4-Kbyte address blocks starting at 0000000H, 0002000H,000

14-7CHIP-SELECT UNITExample 3This example establishes four 2-Kbyte address blocks starting at 2413000H, 2433000H,2613000H, and 2633000H.Because the le

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-8Maximum MemoryAddress2633800HActive 26337FFH2633000H2613FFFH2613800HActive 26137FFH2613000H2433F

14-9CHIP-SELECT UNITExample 4This example establishes two 16-Kbyte address blocks starting at 0E08000H and 0E28000H (16-Kbyte boundaries).Because the

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-1014.3.2 System Management Mode SupportThe processor supports four operating modes: system manage

14-11CHIP-SELECT UNIT14.3.3 Bus Cycle Length ControlEach chip-select channel controls how bus cycles to its address block terminate. Each channel cang

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-12Figure 14-3. Bus Cycle Length Adjustments for Overlapping Regions A2392-02 Complete bus cycl

14-13CHIP-SELECT UNIT14.4 REGISTER DEFINITIONSTable 14-1 and Table 14-2 list the signals and registers associated with the chip-select unit. Thereare

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-14Table 14-2. CSU Registers RegisterExpanded AddressDescriptionPINCFG(read/write)0F826H Pin Confi

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL3-23.2 Intel386 CX PROCESSOR INTERNAL ARCHITECTUREThe internal architecture of the Intel386 CX proce

14-15CHIP-SELECT UNIT14.4.1 Pin Configuration Register (PINCFG)Use PINCFG bits 6 and 4 to connect the CS6# and CS5# signals to package pins.Figure 14-

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-1614.4.2 Port 2 Configuration Register (P2CFG)Use P2CFG bits 4–0 to connect the CS4:0# signals to

14-17CHIP-SELECT UNIT14.4.3 Chip-select Address RegistersThe Address Register of each chip-select channel defines the address block that the channel r

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-18Figure 14-7. Chip-select Low Address Register (CSnADL, UCSADL)Chip-select Low AddressCSnADL (n

14-19CHIP-SELECT UNIT14.4.4 Chip-select Mask RegistersThe Mask Register of each chip-select region is used to prevent bits from being compared withthe

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-20Figure 14-9. Chip-select Low Mask Registers (CSnMSKL, UCSMSKL)Chip-select Low MaskCSnMSKL (n =

14-21CHIP-SELECT UNIT14.5 DESIGN CONSIDERATIONSWhen designing with the CSU, consider the following:• Upon reset, UCS# is configured as a 16-bit chip-s

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL14-2214.6 PROGRAMMING CONSIDERATIONSWhen programming the CSU, consider the following:• When programm

14-23CHIP-SELECT UNITAssumptions:REMAPCFG register has Expanded I/O space access enabled (ESE bit set). */void Init_CSU(void){ _SetEXRegWord(UCSAD

3-3CORE OVERVIEWFigure 3-2 shows the internal architecture of the Intel386 CX processor.Figure 3-2. The Intel386™ CX Processor Internal Block DiagramA

15REFRESH CONTROL UNIT

15-1CHAPTER 15REFRESH CONTROL UNITThe Refresh Control Unit (RCU) simplifies the interface between the processor and a dynamicrandom access memory (DRA

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL15-2The RAS#-only method requires that the DRAM controller activate its RAS# signal when theRCU acti

15-3REFRESH CONTROL UNITFigure 15-1. Refresh Control Unit ConnectionsSystemBusInterval Timer UnitRefresh Clock Interval Register10-bit Interv

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL15-415.2.1 RCU SignalsTable 15-1 describes the signals associated with the RCU.15.2.2 Refresh Interv

15-5REFRESH CONTROL UNITThe 13-bit address counter is a combination of a binary counter and a 7-bit linear-feedback shiftregister. The binary counter

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL15-615.4 REGISTER DEFINITIONSTable 15-2 provides an overview of the registers associated with the RC

15-7REFRESH CONTROL UNIT15.4.1 Refresh Clock Interval Register (RFSCIR)Use RFSCIR to program the interval timer unit’s 10-bit down counter. The refres

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL15-815.4.2 Refresh Control Register (RFSCON)Use RFSCON to enable and disable the refresh control uni

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL3-4The six functional units of the Intel386 CX processor are:• Core Bus Unit• Instruction Prefetch U

15-9REFRESH CONTROL UNIT15.4.3 Refresh Base Address Register (RFSBAD)Use RFSBAD to set up the memory region that needs refreshing. The value written t

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL15-1015.4.4 Refresh Address Register (RFSADD)RFSADD contains the bits A13:1 of the refresh address.

15-11REFRESH CONTROL UNIT15.5 DESIGN CONSIDERATIONSConsider the following when programming the RCU.• The system address bus does not contain an addres

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL15-12• If the counter value stored in the Refresh Clock Interval Register (RFSCIR) is <8 and the

15-13REFRESH CONTROL UNITFigure 15-7. RAS# Only Refresh Logic: Paged ModeNon-page Mode In non-paged mode, the row address buffer can be connected to t

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL15-14Figure 15-8. RAS# Only Refresh Logic: Non-Paged Mode15.6 PROGRAMMING CONSIDERATIONSREFRESH# and

15-15REFRESH CONTROL UNITParameters:Counter_Value Value of the refresh intervalReturns:Error Codes:E_BADVECTOR User input an invalid parameterE_OK Ex

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL15-16Parameters:NoneReturns:Refresh Interval Counter ValueAssumptions: NONESyntax:WO

16INPUT/OUTPUT PORTS

3-5CORE OVERVIEW3.2.4 Execution UnitThe Execution Unit executes the instructions from the Instruction Queue and therefore commu-nicates with all other

16-1CHAPTER 16INPUT/OUTPUT PORTSInput/Output (I/O) ports allow you to transfer information between the processor and the sur-rounding system circuitry

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL16-2Figure 16-1. I/O Port Block Diagram 16.1.1 Port FunctionalityThe function of a bi-directional po

16-3INPUT/OUTPUT PORTSFigure 16-2. Logic Diagram of a Bi-directional Port01SQDQ#CKPnLTCFrom InternalPeripheralRead PortData latchWrite PortData Lat

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL16-4The output of the Pin Configuration latch (PnCFG) selects whether the I/O port or peripheral isc

16-5INPUT/OUTPUT PORTSTable 16-1. Pin Multiplexing Port Pin Peripheral FunctionPin Reset Status(1)Signal Direction(2)InternalPeripheralP1.0 wk 1 DCD0

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL16-616.2 REGISTER DEFINITIONSEach port has three control registers and a status register associated

16-7INPUT/OUTPUT PORTS16.2.1 Pin ConfigurationYou select the operating mode of each pin by writing to the associated bit in the PnCFG registers(Figure

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL16-8Figure 16-4. Port Direction Register (PnDIR)Figure 16-5. Port Data Latch Register (PnLTC)Port DI

16-9INPUT/OUTPUT PORTSFigure 16-6. Port Pin State Register (PnPIN)Port Pin StatePnPIN (n=1–3)(read only)Expanded Addr:ISA Addr:Reset State:F860H, F868

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL16-1016.2.2 Initialization SequenceAfter a device reset, a weak pull-up or pull-down resistor holds

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL3-63.3 CORE Intel386 EX PROCESSOR INTERFACEThe Intel386 EX processor peripherals are connected to th

16-11INPUT/OUTPUT PORTS16.4 PROGRAMMING CONSIDERATIONS16.4.1 I/O Ports Code ExampleThe following code example contains a software routine that initial

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL16-12#define CS2 0x4#define CS3 0x8#define CS4 0X10#define RXD0 0x20#define TXD0 0X40#define

16-13INPUT/OUTPUT PORTS{ /* Select pin values */ _SetEXRegByte(P1LTC, PortLtc1); _SetEXRegByte(P2LTC, PortLtc2); _SetEXRegByte(P3LTC, PortLtc3);

17WATCHDOG TIMER UNIT

17-1CHAPTER 17WATCHDOG TIMER UNITThe watchdog timer (WDT) unit can function as a general-purpose timer, a software watchdogtimer, or a bus monitor, or

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL17-2READY#). In bus monitor mode, the ADS# signal from the bus interface unit (BIU) reloads thedown-

17-3WATCHDOG TIMER UNIT17.1.1 WDT SignalsTable 17-1 describes the signals associated with the WDT. 17.2 WATCHDOG TIMER UNIT OPERATIONAfter a device r

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL17-4The reload registers hold a user-defined value that reloads the down-counter when one of the fol

Intel386™ EX MICROPROCESSOR USER’S MANUALiv4.5.2 Enabling and Disabling the Expanded I/O Space ...4

4SYSTEM REGISTER ORGANIZATION

17-5WATCHDOG TIMER UNIT17.2.3 Software Watchdog ModeIn software watchdog mode, system software must periodically reload the down-counter with areload

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL17-6• To change the reload value, write the new values to the WDTRLDH and WDTRLDL registers, as desc

17-7WATCHDOG TIMER UNIT17.4 REGISTER DEFINITIONSThis section describes the registers associated with the WDT, and explains how these registerscan be u

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL17-8Figure 17-2. WDT Counter Value Registers (WDTCNTH and WDTCNTL)WDT Counter Value (High)WDTCNTH(re

17-9WATCHDOG TIMER UNITFigure 17-3. WDT Status Register (WDTSTATUS)WDT StatusWDTSTATUS(read/write)Expanded Addr:ISA Addr:Reset State:F4CAH—00H7 0WDTEN

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL17-10Figure 17-4. WDT Reload Value Registers (WDTRLDH and WDTRLDL) WDT Reload Value (High)WDTRLDH(re

17-11WATCHDOG TIMER UNITFigure 17-5. Power Control Register (PWRCON)Power Control RegisterPWRCON(read/write)Expanded Addr:ISA Addr:Reset State:F800H—0

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL17-1217.5 DESIGN CONSIDERATIONSThis section outlines design considerations for the watchdog timer un

17-13WATCHDOG TIMER UNITSee Appendix C for included header files.#include <dos.h>#include <conio.h>#include “80386ex.h”#include “ev386ex.h

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL17-14Parameters:NoneReturns:16-bit down-counter valueAssumptions:NoneSyntax:WORD counter_value;count

17-15WATCHDOG TIMER UNIT WDT_BusMonitor(Enable); Real/Protected Mode: No changes required.**********************************************************

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL17-16 routine in Interrupt Vector Table */ Enable8259Interrupt(IR2,IR7); /* Enable

18JTAG TEST-LOGIC UNIT

18-1CHAPTER 18JTAG TEST-LOGIC UNITThe JTAG test-logic unit enables you to test both the device logic and the interconnections be-tween the device and

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL18-2• Place all device output pins into their inactive drive (high-impedance) state, allowing extern

18-3JTAG TEST-LOGIC UNIT18.2 TEST-LOGIC UNIT OPERATION18.2.1 Test Access Port (TAP)The test access port consists of five dedicated pins (four inputs a

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL18-418.2.2 Test Access Port (TAP) ControllerThe TAP controller is a finite-state machine that is cap

18-5JTAG TEST-LOGIC UNITFor example, assume that the TAP controller is in its test-logic-reset state and you want it to startshifting the contents of

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL18-6Figure 18-2. TAP Controller (Finite-State Machine) A2356-01Update -IRExit2 -IRPause -IRExit1

4-1CHAPTER 4SYSTEM REGISTER ORGANIZATIONThis chapter provides an overview of the system registers incorporated in the Intel386™ EX pro-cessor, focusin

18-7JTAG TEST-LOGIC UNIT18.2.3 Instruction Register (IR)An instruction opcode is clocked serially through the TDI pin into the four-bit instruction re

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL18-818.2.4 Data RegistersThe test-logic unit uses three data registers: bypass, identification code,

18-9JTAG TEST-LOGIC UNITThe boundary-scan register (BOUND) holds data to be applied to the pins or data observed at thepins. Each bit corresponds to a

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL18-1018.3 TESTINGThis section explains how to use the test-logic unit to test the device and the boa

18-11JTAG TEST-LOGIC UNITTypically, you would use the SAMPLE/PRELOAD instruction to load data onto the boundary-scan register’s latched parallel outpu

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL18-1218.4 TIMING INFORMATIONThe test-logic unit’s input/output timing is as specified in IEEE 1149.1

18-13JTAG TEST-LOGIC UNITFigure 18-6. Internal and External Timing for Loading a Data Register A2362-01Run - Test / IdleSelect - DR - ScanCapture - DR

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL18-1418.5 DESIGN CONSIDERATIONSThis section outlines considerations for the test-logic unit.• The JT

ASIGNAL DESCRIPTIONS

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-2— Power management control registers— Chip-select unit control registers— Refresh control unit re

A-1APPENDIX ASIGNAL DESCRIPTIONSThis appendix provides reference information for the pins and signals of the device, including thestates of certain pi

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALA-2Table A-2 is an alphabetical list of the signals available at the device pins. The Multiplexed Wi

A-3SIGNAL DESCRIPTIONSCTS1#CTS0#I Clear to Send:Indicates that the modem or data set is ready to exchange data with the SIO channel. EOP#P2.7D15:0 I/O

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALA-4HOLD I Hold Request:An external bus master asserts HOLD to request control of the local bus. The

A-5SIGNAL DESCRIPTIONSP2.7P2.6P2.5P2.4P2.3P2.2P2.1P2.0I/O Port 2:General-purpose, bidirectional I/O port.CTS0#TXD0RXD0CS4#CS3#CS2#CS1#CS0#P3.7P3.6P3.5

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALA-6SMI# ST System Management Interrupt:Causes the device to enter System Management Mode. SMI# is th

A-7SIGNAL DESCRIPTIONSTMS I Test Mode Select:Controls the sequence of the test-logic unit’s TAP controller states. Sampled on the rising edge of TCK.—

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALA-8Table A-3 defines the abbreviations used in Table A-4 to describe the pin states.Table A-3. Pin S

A-9SIGNAL DESCRIPTIONSTable A-4 lists the states of output and bidirectional pins after reset and during idle mode, pow-erdown, and hold. Table A-4. P

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALA-10The following input pins have permanent weak pull-up resistors: TCK, TDI, TMS, TRST#,SMI#, PEREQ

4-3SYSTEM REGISTER ORGANIZATIONFigure 4-1. PC/AT I/O Address Space (10-bit Decode) 4.3 EXPANDED I/O ADDRESS SPACEThe Intel386 EX processor’s I/O addre

BCOMPATIBILITY WITH THE PC/AT* ARCHITECTURE

B-1APPENDIX BCOMPATIBILITY WITH THE PC/AT*ARCHITECTUREThe Intel386™ EX embedded processor is NOT 100% PC/AT* compatible. Due to compatibilityissues, n

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALB-2To eliminate these problems with an 8237A DMA controller, the Intel386 EX processor inte-grates a

B-3COMPATIBILITY WITH THE PC/AT* ARCHITECTUREFigure B-1. Derivation of AEN Signal in a Typical PC/AT SystemFor systems based on Intel386 EX processor,

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALB-4the Intel386 EX embedded processor) demonstrates the design of a Synchronous Expansion Busthat is

B-5COMPATIBILITY WITH THE PC/AT* ARCHITECTUREB.1.7 Port BThe Port B register found on the PC/AT is not supported on the Intel386 EX processor. It can

CEXAMPLE CODE HEADER FILES

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-4(See Figure 4-2.) Thus, each slot has 1 Kbyte addresses (in four 256-byte segments) that can po-t

C-1APPENDIX CEXAMPLE CODE HEADER FILESThis appendix contains the header files called by the code examples that are included in severalchapters of this

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALC-2#define OCW2SDOS 0x00A0#define OCW3MDOS 0x0020#define OCW3SDOS 0x00A0/* CONFIGURATION Re

C-3EXAMPLE CODE HEADER FILES#define IIR0 0xF4FA#define LCR0 0xF4FB#define MCR0 0xF4FC#define LSR0 0xF4FD#define MSR0

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALC-4#define SSIOCON2 0xF488#define SSIOCTR 0xF48A/* CHIP SELECT UNIT Registers */#define CS0AD

C-5EXAMPLE CODE HEADER FILES#define DMACMD1 0xF008#define DMASTS 0xF008#define DMASRR 0xF009#define DMAMSK 0xF00A#define DMAMOD1

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALC-6C.2 EXAMPLE CODE DEFINES/*********************** Global typedef **********************/typedef un

C-7EXAMPLE CODE HEADER FILES#define MPIN_INT0 0x4#define MPIN_INT1 0x8#define MPIN_INT2 0x10#define MPIN_INT3 0x20/* ICU Master External Cascade IRs *

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALC-8 /************ Asynchronous Serial I/O Port defines ***********/#define SIO_0 0#define SIO_1

C-9EXAMPLE CODE HEADER FILES#define SIO_TX_EMPTY 0x40/* Offsets from beginning of SIO port addresses */#define RBR 0#define TBR 0#define DLL 0#define

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALC-10typedef enum{ DMA_Channel0 = 0, DMA_Channel1 = 1} DMAChannelEnum;typedef enum{

4-5SYSTEM REGISTER ORGANIZATIONThe Intel386 EX processor uses slot 15 for the registers needed for integrated peripherals. Usingthis slot avoids confl

C-11EXAMPLE CODE HEADER FILES#define P1_IN 0x2#define P2_IN 0x4#define P3_IN 0x8#define P4_IN 0x10#define P5_IN 0x20#define P6_IN 0x40#define P7_IN 0x

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALC-12#define TMR_GATE_EXTRN 0x2#define TMR_OUT_ENABLE 0x1#define TMR_OUT_DISABLE 0#define TMR_ENA

C-13EXAMPLE CODE HEADER FILESBYTE PreScale);extern WORD SSerialReadWord(BYTE MasterSlave);extern void SSerialWriteWord(WORD Ch,BYTE MasterSlave);void

DSYSTEM REGISTER QUICK REFERENCE

D-1APPENDIX DSYSTEM REGISTER QUICK REFERENCED.1 PERIPHERAL REGISTER ADDRESSESTable D-1. Peripheral Register Addresses (Sheet 1 of 6)Expanded AddressPC

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-2F019H Byte DMACHR/DMAIS 00HF01AH Byte DMACMD2 08HF01BH Byte DMAMOD2 00HF01CH Byte DMAIEN 00HF01DH

D-3SYSTEM REGISTER QUICK REFERENCEF08EH ReservedF08FH ReservedF098H Byte DMA0BYC2 XXF099H Byte DMA1BYC2 XXF09AH ReservedF09BH ReservedA20GATE and Fast

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-4F426H Word CS4MSKH 0000HF428H Word CS5ADL 0000HF42AH Word CS5ADH 0000HF42CH Word CS5MSKL 0000HF42

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-64.5 I/O ADDRESS DECODING TECHNIQUESOne of the key features of the Intel386 EX processor is that i

D-5SYSTEM REGISTER QUICK REFERENCEAsynchronous Serial I/O Channel 0 (COM1)F4F8H 03F8H Byte RBR0/TBR0/DLL0 XX/XX/02HF4F9H 03F9H Byte IER0/DLH0 00H/00HF

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-6Asynchronous Serial I/O Channel 1 (COM2)F8F8H 02F8H Byte RBR1/TBR1/DLL1 XX/XX/02HF8F9H 02F9H Byte

D-7SYSTEM REGISTER QUICK REFERENCED.2 CLKPRSClock Prescale RegisterCLKPRS(read/write)Expanded Addr:ISA Addr:Reset State:F804H—0000H15 8———— ———PS87 0P

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-8D.3 CSnADH (UCSADH)Chip-select High AddressCSnADH (n = 0–6), UCSADH(read/write)Expanded Addr:ISA

D-9SYSTEM REGISTER QUICK REFERENCED.4 CSnADL (UCSADL)Chip-select Low AddressCSnADL (n = 0–6), UCSADL(read/write)Expanded Addr:ISA Addr:Reset State:F40

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-10D.5 CSnMSKH (UCSMSKH)Chip-select High MaskCSnMSKH (n = 0–6), UCSMSKH(read/write)Expanded Addr:IS

D-11SYSTEM REGISTER QUICK REFERENCED.6 CSnMSKL (UCSMSKL)Chip-select Low MaskCSnMSKL (n = 0–6), UCSMSKL(read/write)Expanded Addr:ISA Addr:Reset State:F

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-12D.7 DLLn AND DLHnDivisor Latch LowDLL0, DLL1(read/write)Expanded Addr:ISA Addr:Reset State:DLL0

D-13SYSTEM REGISTER QUICK REFERENCED.8 DMABSRDMA Bus SizeDMABSR(write only)Expanded Addr:ISA Addr:Reset State:F018H—X1X10000B7 0—RBS—TBS—— 0CSBit Numb

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-14D.9 DMACFGDMA ConfigurationDMACFG(read/write)Expanded Addr:ISA Addr:Reset State:F830H—00H7 0D1MS

4-7SYSTEM REGISTER ORGANIZATIONFigure 4-3. Address Configuration Register (REMAPCFG)Address Configuration RegisterREMAPCFGExpanded Addr:PC/AT Address:

D-15SYSTEM REGISTER QUICK REFERENCED.10 DMACHRDMA ChainingDMACHR(write only)Expanded Addr:ISA Addr:Reset State:F019H—00H7 0———— —CE0CSBit NumberBit Mn

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-16D.11 DMACMD1DMA Command 1DMACMD1(write only)Expanded Addr:ISA Addr:Reset State:F008H0008H00H7 0—

D-17SYSTEM REGISTER QUICK REFERENCED.12 DMACMD2DMA Command 2DMACMD2(write only)Expanded Addr:ISA Addr:Reset State:F01AH—08H7 0— — — — PL1 PL0 ES DSBit

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-18D.13 DMAGRPMSKDMA Group Channel MaskDMAGRPMSK(read/write)Expanded Addr:ISA Addr:Reset State:F00F

D-19SYSTEM REGISTER QUICK REFERENCED.14 DMAIENDMA Interrupt EnableDMAIEN(read/write)Expanded Addr:ISA Addr:Reset State:F01CH—00H7 0———— ——TC1TC0Bit Nu

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-20D.15 DMAISDMA Interrupt StatusDMAIS(read only)Expanded Addr:ISA Addr:Reset State:F019H—00H7 0——T

D-21SYSTEM REGISTER QUICK REFERENCED.16 DMAMOD1DMA Mode 1DMAMOD1(write only)Expanded Addr:ISA Addr:Reset State:F00BH000BH00H7 0DTM1 DTM0 TI AI TD1 TD0

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-22D.17 DMAMOD2DMA Mode 2DMAMOD2(write only)Expanded Addr:ISA Addr:Reset State:F01BH—00H7 0BCO RD T

D-23SYSTEM REGISTER QUICK REFERENCED.18 DMAMSKDMA Individual Channel MaskDMAMSK(write only)Expanded Addr:ISA Addr:Reset State:F00AH000AH04H7 0———— —HR

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-24D.19 DMAnBYCn, DMAnREQn AND DMAnTARnDMA Channel 0DMA Channel 124 16 8 0Requester Address DMA0REQ

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-84.5.2 Enabling and Disabling the Expanded I/O SpaceThe Intel386 EX processor’s expanded I/O space

D-25SYSTEM REGISTER QUICK REFERENCED.20 DMAOVFEDMA Overflow EnableDMAOVFE(read/write)Expanded Addr:ISA Addr:Reset State:F01DH—0AH7 0— — — — ROV1 TOV1

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-26D.21 DMASRRDMA Software Request (read format)DMASRRExpanded Addr:ISA Addr:Reset State:F009H0009H

D-27SYSTEM REGISTER QUICK REFERENCED.22 DMASTSDMA StatusDMASTS(read only)Expanded Addr:ISA Addr:Reset State:F008H0008H00H7 0— — R1 R0 — — TC1 TC0Bit N

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-28D.23 ICW1 (MASTER AND SLAVE)Initialization Command Word 1ICW1 (master and slave)(write only)Expa

D-29SYSTEM REGISTER QUICK REFERENCED.24 ICW2 (MASTER AND SLAVE)D.25 ICW3 (MASTER)Initialization Command Word 2ICW2 (master and slave)(write only)Expan

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-30D.26 ICW3 (SLAVE)D.27 ICW4 (MASTER AND SLAVE)Initialization Command Word 3ICW3 (slave)(write onl

D-31SYSTEM REGISTER QUICK REFERENCED.28 IDCODEIdentification Code RegisterIDCODE Reset State:2027 0013H (3V)2827 0013H (5V)31 2400100 (3V)1 (5V)00023

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-32D.29 IERnInterrupt EnableIER0, IER1(read/write)Expanded Addr:ISA Addr:Reset State:IER0 IER1F4F9H

D-33SYSTEM REGISTER QUICK REFERENCED.30 IIRnInterrupt IDIIR0, IIR1(read only)Expanded Addr:ISA Addr:Reset State:IIR0 IIR1F4FAH F8FAH03FAH 02FAH01H 01H

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-34D.31 INTCFGInterrupt ConfigurationINTCFG(read/write)Expanded Addr:ISA Addr:Reset State:F832H—00H

vCONTENTS6.3.4 Interrupt Acknowledge Cycle ...6-236.3.5 Halt/Shutdown

4-9SYSTEM REGISTER ORGANIZATION4.6 ADDRESSING MODESCombinations of the value of ESE bit and the individual remap bits in the REMAPCFG registeryield fo

D-35SYSTEM REGISTER QUICK REFERENCED.32 IRInstruction RegisterIRReset State(Using TRST#): 02H3 0INST3 INST2 INST1 INST0Bit NumberBit MnemonicFunction3

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-36D.33 LCRnSerial Line ControlLCR0, LCR1(read/write)Expanded Addr:ISA Addr:Reset State:LCR0 LCR1F4

D-37SYSTEM REGISTER QUICK REFERENCED.34 LSRnSerial Line StatusLSR0, LSR1(read only)Expanded Addr:ISA Addr:Reset State:LSR0 LSR1F4FDH F8FDH03FDH 02FDH

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-38D.35 MCRnModem ControlMCR0, MCR1(read/write)Expanded Addr:ISA Addr:Reset State:MCR0 MCR1F4FCH F8

D-39SYSTEM REGISTER QUICK REFERENCED.36 MSRnModem StatusMSR0, MSR1(read only)Expanded Addr:ISA Addr:Reset State:MSR0 MSR1F4FEH F8FEH03FEH 02FEHX0H X0H

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-40D.37 OCW1 (MASTER AND SLAVE)Operation Command Word 1OCW1 (master and slave)(read/write)Expanded

D-41SYSTEM REGISTER QUICK REFERENCED.38 OCW2 (MASTER AND SLAVE)Operation Command Word 2OCW2 (master and slave)(write only)Expanded Addr:ISA Addr:Reset

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-42D.39 OCW3 (MASTER AND SLAVE)Operation Command Word 3OCW3 (master and slave)(write only)Expanded

D-43SYSTEM REGISTER QUICK REFERENCED.40 P1CFGPort 1 ConfigurationP1CFG(read/write)Expanded Addr:ISA Addr:Reset State:F820H—00H7 0PM7 PM6 PM5 PM4 PM3 P

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-44D.41 P2CFGPort 2 ConfigurationP2CFG(read/write)Expanded Addr:ISA Addr:Reset State:F822H—00H7 0PM

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-10Figure 4-5. DOS-Compatible Mode 3FFH23H22HOn-chip UART-0On-chip UART-1On-chip 8259A-2On-chip Tim

D-45SYSTEM REGISTER QUICK REFERENCED.42 P3CFGPort 3 ConfigurationP3CFG(read/write)Expanded Addr:ISA Addr:Reset State:F824H—00H7 0PM7 PM6 PM5 PM4 PM3 P

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-46D.43 PINCFGPin ConfigurationPINCFG(read/write)Expanded Addr:ISA Addr:Reset State:F826H—00H7 0— P

D-47SYSTEM REGISTER QUICK REFERENCED.44 PnDIRPort DIrectionPnDIR (n=1–3)(read/write)Expanded Addr:ISA Addr:Reset State:F864H, F86CH, F874H—FFH7 0PD7 P

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-48D.45 PnLTCD.46 PnPINPort Data LatchPnLTC (n=1–3)(read/write)Expanded Addr:ISA Addr:Reset State:F

D-49SYSTEM REGISTER QUICK REFERENCED.47 POLL (MASTER AND SLAVE)Poll Status BytePOLL (master and slave)(read only)Expanded Addr:ISA Addr:Reset State:ma

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-50D.48 PORT92Port 92 ConfigurationPORT92(read/write)Expanded Addr:ISA Addr:Reset State:F092H0092HX

D-51SYSTEM REGISTER QUICK REFERENCED.49 PWRCONPower Control RegisterPWRCON(read/write)Expanded Addr:ISA Addr:Reset State:F800H—00H7 0— — — — WDTRDY HS

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-52D.50 RBRnReceive BufferRBR0, RBR1(read only)Expanded Addr:ISA Addr:Reset State:RBR0 RBR1F4F8H F8

D-53SYSTEM REGISTER QUICK REFERENCED.51 REMAPCFGAddress Configuration RegisterREMAPCFGExpanded Addr:PC/AT Address:Reset State:0022H0022H0000H15 8ESE——

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-54D.52 RFSADDD.53 RFSBADRefresh AddressRFSADD(read/write)Expanded Addr:ISA Addr:Reset State:F4A6H—

4-11SYSTEM REGISTER ORGANIZATION4.6.2 Nonintrusive DOS ModeThis mode is achieved by first setting the ESE bit (using the three sequential writes), set

D-55SYSTEM REGISTER QUICK REFERENCED.54 RFSCIRD.55 RFSCONRefresh Clock IntervalRFSCIR(read/write)Expanded Addr:ISA Addr:Reset State:F4A2H—0000H15 8———

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-56D.56 SCRnScratch PadSCR0, SCR1(read/write)Expanded Addr:ISA Addr:Reset State:SCR0 SCR1F4FFH F8FF

D-57SYSTEM REGISTER QUICK REFERENCED.57 SIOCFGSIO and SSIO ConfigurationSIOCFG(read/write)Expanded Addr:ISA Addr:Reset State:F836H—00H7 0S1M S0M — — —

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-58D.58 SSIOBAUDSSIO Baud-rate ControlSSIOBAUD(read/write)Expanded Addr:ISA Addr:Reset State:F484H—

D-59SYSTEM REGISTER QUICK REFERENCED.59 SSIOCON1SSIO Control 1SSIOCON1(read/write)Expanded Addr:ISA Addr:Reset State:F486H—C0H7 0TUE THBE TIE TEN ROE

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-60D.60 SSIOCON2SSIO Control 2SSIOCON2(read/write)Expanded Addr:ISA Addr:Reset State:F488H—00H7 0——

D-61SYSTEM REGISTER QUICK REFERENCED.61 SSIOCTRD.62 SSIORBUFBaud-rate Count DownSSIOCTR(read only)Expanded Addr:ISA Addr:Reset State:F48AH—00H7 0BSTAT

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-62D.63 SSIOTBUFD.64 TBRnTransmit Holding BufferSSIOTBUF(read/write)Expanded Addr:ISA Addr:Reset St

D-63SYSTEM REGISTER QUICK REFERENCED.65 TMRCFG.Timer ConfigurationTMRCFG(read/write)Expanded Addr:ISA Addr:Reset State:F834H—00H7 0TMRDIS SWGTEN GT2CO

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-64D.66 TMRCONTimer Control (Control Word Format)TMRCONExpanded Addr:ISA Addr:Reset State:F043H0043

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-12Figure 4-6. Example of Nonintrusive DOS-Compatible Mode 3FFH0Internal DMA0HOn-chip 8259A-1On-chi

D-65SYSTEM REGISTER QUICK REFERENCED.67 TMRnTimer n (Read Format)TMRn (n = 0–2)Expanded Addr:ISA Addr:Reset State:F040H, F041HF042H0040H, 0041H0042HXX

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-66Timer n (Status Format)TMRn (n = 0–2)Expanded Addr:ISA Addr:Reset State:F040H, F041HF042H0040H,

D-67SYSTEM REGISTER QUICK REFERENCED.68 UCSADHSee “CSnADH (UCSADH)” on page D-8.D.69 UCSADLSee “CSnADL (UCSADL)” on page D-9.D.70 UCSMSKHSee “CSnMSKH

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-68D.72 WDTCNTH AND WDTCNTLWDT Counter Value (High)WDTCNTH(read only)Expanded Addr:ISA Addr:Reset S

D-69SYSTEM REGISTER QUICK REFERENCED.73 WDTRLDH AND WDTRLDLWDT Reload Value (High)WDTRLDH(read/write)Expanded Addr:ISA Addr:Reset State:F4C0H—003FH15

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALD-70D.74 WDTSTATUS.WDT StatusWDTSTATUS(read/write)Expanded Addr:ISA Addr:Reset State:F4CAH—00H7 0WDT

EINSTRUCTION SET SUMMARY

E-1APPENDIX EINSTRUCTION SET SUMMARYThis appendix provides reference information for the Intel386™ processor family instruction set. The appendix is o

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-2Wait states:Wait states add 1 clock per wait state to instruction execution for each data access.

4-13SYSTEM REGISTER ORGANIZATIONFigure 4-7. Enhanced DOS Mode 3FFH0On-chip DMA0HOn-chip 8259A-1On-chip UART-2On-chip UART-1On-chip 8259A-2On-chip Time

E-3INSTRUCTION SET SUMMARYimmediate 0 1 1 0 1 0 s 0 immediate data 24bhPUSHA = Push All 0 1 1 0 0 0 0 0 18 34 b hPOP = Popregister/memory 1 0 0 0 1 1

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-4CLD = Clear direction flag1 1 1 1 1 1 0 022CLI = Clear interrupt enable flag1 1 1 1 1 0 1 088 mCL

E-5INSTRUCTION SET SUMMARYSUB = Subtractregister from register 0 0 1 0 1 0 d w mod reg r/m 2 2register from memory 0 0 1 0 1 0 0 w mod reg r/m 7** 7**

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-6MUL = multiply (unsigned)accumulator with register/memory1 1 1 1 0 1 1 w mod 1 0 0 r/mmultiplier—

E-7INSTRUCTION SET SUMMARYIDIV = Integer divide (signed)Accumulator by register/memory1 1 1 1 0 1 1 w mod 111 r/mdivisor— byte— word— doubleword19/222

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-8SHRD = Shift right doubleregister/memory by immediate0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 mod reg r/mi

E-9INSTRUCTION SET SUMMARYSTRING MANIPULATION INSTRUCTIONS Clk Count Virtual 8086 ModeCMPS = Compare byte word1 0 1 0 0 1 1 w10* 10* b hINS = Input by

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-10register/memory, register0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 mod reg r/m3/12* 3/12* b hBTC = test b

E-11INSTRUCTION SET SUMMARYVia call gate to different privilege level (no parameters) 102 + m h, j, k, rVia call gate to different privilege level (x

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-12within segment adding immed to SP1 1 0 0 0 0 1 0 16-bit displacement12 + m b g, h, rintersegment

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-14Figure 4-8. NonDOS Mode 3FFH0H0101111 0118259A-18259A-2TimerUART-1UART-0On-chip DMAOther Periphe

E-13INSTRUCTION SET SUMMARYFull displacement0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 1 Full displacement7 + m or 37 + m or 3rJBE/JNA = jump on below or equal/not

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-14Full displacement0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 Full displacement7 + m or 37 + m or 3rJLE/JNG =

E-15INSTRUCTION SET SUMMARYSETBE/SETNA = set byte on below or equal/not aboveto register/memory 0 0 0 0 1 1 1 1 1 0 0 1 0 1 1 0 mod 0 0 0 r/m 4/5* 4/5

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-16BOUND = Interrupt 5 if Detect value out of range0 1 1 0 0 0 1 0 mod reg r/mIf out of range 44 b,

E-17INSTRUCTION SET SUMMARYINTO:Via interrupt or Trap GateTo same privilege level71 g, j, k, rVia Interrupt or Trap GateTo different privilege level11

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-18To different privilege level (within task) 86 g, h, j, k, rFrom 286 task to 286 TSS 285 g, h, j

E-19INSTRUCTION SET SUMMARYPREFIX BYTESAddress size prefix 0 1 1 0 0 1 1 1 0 0LOCK = Bus lock prefix 1 1 1 1 0 0 0 0 0 0 mOperand size prefix 0 1 1 0

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-20NOTES:Notes a through c apply to Real Address Mode only:a. This is a Protected Mode instruction.

E-21INSTRUCTION SET SUMMARYb = 10 for register with immediate to registerb = 11 for memory with immediate to register.e. An exception may occur, depen

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-22E.2 INSTRUCTION ENCODINGAll instruction encodings are subsets of the general instruction format

4-15SYSTEM REGISTER ORGANIZATION4.7 PERIPHERAL REGISTER ADDRESSESTable 4-2 lists the addresses and names of all user-accessible peripheral registers.

E-23INSTRUCTION SET SUMMARYE.2.1 32-bit Extensions of the Instruction SetWith the Intel386 EX processor the 8086/80186/80286 instruction set is extend

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-24Unless specified otherwise, instructions with 8-bit and 16-bit operands do not affect the conten

E-25INSTRUCTION SET SUMMARYE.2.2.3 Encoding of the Segment Register (sreg) FieldThe sreg field in certain instructions is a 2-bit field allowing one o

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-26E.2.2.4 Encoding of Address ModeExcept for special instructions, such as PUSH or POP, where the

E-27INSTRUCTION SET SUMMARYTable E-7. Encoding of 16-bit Address Mode with “mod r/m” Bytemod r/m Effective Address mod r/m Effective Address00 00000 0

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-28Table E-8. Encoding of 32-bit Address Mode with “mod r/m” Byte (No s-i-b Byte Present)mod r/m Ef

E-29INSTRUCTION SET SUMMARYTable E-9. Encoding of 32-bit Address Mode (“mod r/m” Byte and s-i-b Byte Present)mod r/m Effective Address00 00000 00100 0

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALE-30E.2.2.5 Encoding of Operation Direction (d) FieldIn many two-operand instructions the d field is

E-31INSTRUCTION SET SUMMARYE.2.2.8 Encoding of Control or Debug or Test Register (eee) FieldFor the loading and storing of the Control, Debug and Test

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-16F018H Byte DMABSR X1X10000BF019H Byte DMACHR/DMAIS 00HF01AH Byte DMACMD2 08HF01BH Byte DMAMOD2 0

GLOSSARY

Glossary-1GLOSSARYThis glossary defines acronyms, abbreviations, and terms that have special meaning in this man-ual. (Chapter 1, GUIDE TO THIS MANUAL

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALGlossary-2be mapped into this space. In this manual, the terms DOS address and PC/AT address are syn

Glossary-3GLOSSARYInterrupt Response Time The amount of time required to complete an interrupt acknowledge cycle and transfer program control to the i

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUALGlossary-4PC/AT Address Space Addresses 0H–03FFH. The internal timers, interrupt controller, serial

Glossary-5GLOSSARYcommunications. The transmitter and receiver can operate independently (with different clocks) to provide full-duplex communication.

Index

4-17SYSTEM REGISTER ORGANIZATIONF08DH ReservedF08EH ReservedF08FH ReservedF098H Byte DMA0BYC2 XXF099H Byte DMA1BYC2 XXF09AH ReservedF09BH ReservedA20G

Index-1#, defined, 1-382C59A, 9-1AAddress bus, 6-1Address linesnew,3-1Address spaceconfiguration register,4-6expanded I/O, 4-3enabling/disabling, 4-8I

INTEL386™ EX MICROPROCESSOR USER’S MANUALIndex-2operation during idle mode, 8-5overview, 6-1–6-3pipelining, 6-8ready logic, 6-10See also Bus control a

Index-3INDEXDDeassert, defined, 1-4Decoding techniques, I/O address, 4-6Design considerationsclock and power management unit,8-11input/output ports, 1

INTEL386™ EX MICROPROCESSOR USER’S MANUALIndex-4DOS compatibilitydepartures from PC/AT architecturebus signals,B-2CPU-only reset, B-4DMA unit, B-1HOLD

Index-5INDEXoperation, 9-4–9-16overview, 9-1programming, 9-15–9-32considerations, 9-32ICW1, 9-20, D-28ICW1 register, 9-20ICW2, 9-21, D-29ICW2 register

INTEL386™ EX MICROPROCESSOR USER’S MANUALIndex-6register locations, 4-5, 4-15Peripherals, summary, 2-3Physical address space, 3-1Pin configuration, 5-

Index-7INDEXregister addresses, 4-18, D-4registers, 15-6signals, 15-4Registernaming conventions,1-4organization, 4-1–4-20Register bits, notational con

INTEL386™ EX MICROPROCESSOR USER’S MANUALIndex-8SSIOTBUF, 13-16, 13-24, D-61TBRn, 11-15, 11-23, D-61TMRCFG,5-13, 10-4, 10-21, D-62TMRCON, 10-4, 10-25,

Index-9INDEXoperation, 13-5–13-15baud-rate generator, 13-5–13-6receiver, 13-12–13-15transmitter, 13-6overview, 13-1–13-4programming, 13-16–13-25CLKPRS

INTEL386™ EX MICROPROCESSOR USER’S MANUALIndex-10mode 3, 10-12–10-15basic operation, 10-13–10-14basic operation (odd count), 10-14disabling the count,

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-18F424H Word CS4MSKL 0000HF426H Word CS4MSKH 0000HF428H Word CS5ADL 0000HF42AH Word CS5ADH 0000HF4

Index-11INDEXregisters, 17-7WDTCLR, 17-7WDTCNTH, 17-7WDTCNTL, 17-7WDTRLDH, 17-7WDTRLDL, 17-7WDTSTATUS, 17-7reload event, 17-4signals, 17-3WDT, See Wat

Intel386™ EX MICROPROCESSOR USER’S MANUALvi7.3.4.2 SMRAM State Dump Area ...

4-19SYSTEM REGISTER ORGANIZATIONF4CAH Byte WDTSTATUS 00HAsynchronous Serial I/O Channel 0 (COM1)F4F8H 03F8H Byte RBR0/TBR0/DLL0 XX/XX/02HF4F9H 03F9H B

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL4-20Asynchronous Serial I/O Channel 1 (COM2)F8F8H 02F8H Byte RBR1/TBR1/DLL1 XX/XX/02HF8F9H 02F9H Byt

5DEVICE CONFIGURATION

5-1CHAPTER 5DEVICE CONFIGURATIONThe Intel386™ EX processor provides many possible signal to pin connections as well as periph-eral to peripheral conne

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-2Figure 5-1 shows Peripheral A and its connections to other peripherals and the package pins. The“

5-3DEVICE CONFIGURATION5.2 PERIPHERAL CONFIGURATIONThis section describes the configuration of each on-chip peripheral. For more detailed informa-tion

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-4configured DMA channel. SIO and SSIO inputs to the DMA are selected by the DMA configu-ration reg

5-5DEVICE CONFIGURATIONFigure 5-2. Configuration of DMA, Bus Arbiter, and Refresh UnitA2516-02DREQ0DMAACK0#DREQ1DMAACK1#DMAINTDMABus ArbiterRefresh Un

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-6Figure 5-3. DMA Configuration Register (DMACFG)DMA ConfigurationDMACFG(read/write)Expanded Addr:I

viiCONTENTS9.3.3 Initialization Command Word 1 (ICW1) ...9-209.3.4 Initialization Comm

5-7DEVICE CONFIGURATION5.2.2 Interrupt Control Unit ConfigurationThe interrupt control unit (ICU) comprises two 82C59A interrupt controllers connected

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-8Table 5-1. Master’s IR3 ConnectionsFunction INTCFG.6 MCR1.3 P3CFG.1IR3 connected to SIOINT1P3.1 s

5-9DEVICE CONFIGURATIONFigure 5-4. Interrupt Control Unit ConfigurationIR0IR1IR28259AMasterIR401INT0(P3.2)†To/From I/O Port 3P3CFG.2VSSP3CFG.2IR5IR6

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-10Figure 5-5. Interrupt Configuration Register (INTCFG)Interrupt ConfigurationINTCFG(read/write)Ex

5-11DEVICE CONFIGURATION5.2.3 Timer/counter Unit ConfigurationThe three-channel Timer/counter Unit (TCU) and its configuration register (TMRCFG) aresh

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-12Figure 5-6. Timer/Counter Unit ConfigurationA2517-03CLKIN0GATE0OUT0GATE1Timer/CounterUnitCLKIN1

5-13DEVICE CONFIGURATION.Figure 5-7. Timer Configuration Register (TMRCFG)Timer ConfigurationTMRCFG(read/write)Expanded Addr:ISA Addr:Reset State:F834

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-145.2.4 Asynchronous Serial I/O ConfigurationFigures 5-8 and 5-9 show the asynchronous serial I/O

5-15DEVICE CONFIGURATIONFigure 5-8. Serial I/O Unit 0 ConfigurationTo DMATXEDMA0To ICUSIOINT0A2521-02BCLKINReceive DataTransmit DataRequest to SendSIO

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-16Figure 5-9. Serial I/O Unit 1 ConfigurationA2519-02BCLKINReceive DataTransmit DataRequest to Sen

Intel386™ EX MICROPROCESSOR USER’S MANUALviiiCHAPTER 11ASYNCHRONOUS SERIAL I/O UNIT11.1 OVERVIEW ...

5-17DEVICE CONFIGURATIONFigure 5-10. SIO and SSIO Configuration Register (SIOCFG)SIO and SSIO ConfigurationSIOCFG(read/write)Expanded Addr:ISA Addr:Re

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-185.2.5 Synchronous Serial I/O ConfigurationThe synchronous serial I/O unit (SSIO) is shown in Fig

5-19DEVICE CONFIGURATION5.2.6 Chip-select Unit and Clock and Power Management Unit ConfigurationFigure 5-12 shows the multiplexing of signals of the C

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-20Figure 5-12. Configuration of Chip-select Unit and Clock and Power Management UnitA3380-01CS0#C

5-21DEVICE CONFIGURATION5.2.7 Core ConfigurationThree coprocessor signals (ERROR#, PEREQ, and BUSY# in Figure 5-13) can be routed to thecore, as deter

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-22Setting bit 0 in the PORT92 register (see Figure 5-14) resets the core without resetting the per

5-23DEVICE CONFIGURATION5.3 PIN CONFIGURATIONMost of the microprocessor’s package pins support two peripheral functions. Some of these pinsare routed

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-24Figure 5-15. Pin Configuration Register (PINCFG)Pin ConfigurationPINCFG(read/write)Expanded Addr

5-25DEVICE CONFIGURATIONFigure 5-16. Port 1 Configuration Register (P1CFG)Port 1 ConfigurationP1CFG(read/write)Expanded Addr:ISA Addr:Reset State:F820

Intel386™ EX EMBEDDED MICROPROCESSOR USER’S MANUAL5-26Figure 5-17. Port 2 Configuration Register (P2CFG)Port 2 ConfigurationP2CFG(read/write)Expanded