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Processor Configuration Registers

276 Datasheet, Volume 2

2.18.17 PHMBASE_REG—Protected High Memory Base Register

This register is used to set up the base address of DMA-protected high-memory region.

This register must be set up before enabling protected memory through PMEN_REG,

and must not be updated when protected memory regions are enabled.

When the LT CMD.LOCK.PMRC command is invoked, this register is locked (treated as

RO). When the LT CMD.UNLOCK.PMRC command is invoked, this register is unlocked

(treated as RW).

This register is always treated as RO for implementations not supporting protected high

memory region (PHMR field reported as 0 in the Capability register).

The alignment of the protected high memory region base depends on the number of

reserved bits (N:0) of this register. Software may determine N by writing all 1s to this

in the value read back from the register. Bits N:0 of this register are decoded by

hardware as all 0s.

Software may setup the protected high memory region either above or below 4 GB.

B/D/F/Type: 0/2/0/GFXVTBAR

Address Offset: 70–77h

Reset Value: 0000000000000000h

Access: RO, RW

Bit Attr

Reset

Value

Description

63:36 RO 0000000h Reserved

35:21 RW 0000h

Protected High-Memory Base (PHMB)

This register specifies the base of protected (high) memory region in system

memory.

Hardware ignores, and does not implement, bits 63:HAW, where HAW is the

host address width.

20:0 RO 000000h Reserved

1 2 ... 271 272 273 274 275 276 277 278 279 280 281 ... 359 360

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