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Datasheet, Volume 2 235
Processor Configuration Registers
2.16.9 FECTL_REG—Fault Event Control Register
This register specifies the fault event interrupt message control bits. The VTd
specification describes hardware handling of fault events.
B/D/F/Type: 0/0/0/DMIVC1REMAP
Address Offset: 38-3Bh
Reset Value: 80000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
31 RW 1b
Interrupt Mask (IM)
0 = No masking of interrupt. When a interrupt condition is detected,
hardware issues an interrupt message (using the Fault Event Data &
Fault Event Address register values).
1 = This is the value on reset. Software may mask interrupt message
generation by setting this field. Hardware is prohibited from sending the
interrupt message when this field is set.
30 RO 0b
Interrupt Pending (IP)
Hardware sets the IP field whenever it detects an interrupt condition, which is
defined as:
• When primary fault logging is active, an interrupt condition occurs when
hardware records a fault through one of the Fault Recording registers
and sets the PPF field in the Fault Status register.
• When advanced fault logging is active, an interrupt condition occurs
when hardware records a fault in the first fault record (at index 0) of the
current fault log and sets the APF field in the Fault Status register.
• Hardware detected error associated with the Invalidation Queue, setting
the IQE field in the Fault Status register.
• Hardware detected invalid Device-IOTLB invalidation completion, setting
the ICE field in the Fault Status register.
• Hardware detected Device-IOTLB invalidation completion time-out,
setting the ITE field in the Fault Status register.
If any of the status fields in the Fault Status register was already Set at the
time of setting any of these fields, it is not treated as a new interrupt
condition.
The IP field is kept Set by hardware while the interrupt message is held
pending. The interrupt message could be held pending due to the interrupt
mask (IM field) being Set or other transient hardware conditions.
The IP field is cleared by hardware as soon as the interrupt message pending
condition is serviced.
This could be due to either:
• Hardware issuing the interrupt message due to either a change in the
transient hardware condition that caused the interrupt message to be
held pending, or due to software clearing the IM field.
• Software servicing all the pending interrupt status fields in the Fault
Status register as follows.
— When primary fault logging is active, software clearing the Fault
(F) field in all the Fault Recording registers with faults, causing the
PPF field in the Fault Status register to be evaluated as Clear.
— Software clearing other status fields in the Fault Status register by
writing back the value read from the respective fields.
29:0 RO 00..00h Reserved
- Datasheet – Volume 2 1
- Legal Lines and Disclaimers 2
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- 10 Datasheet, Volume 2 10
- Datasheet, Volume 2 11 11
- Revision History 12
- 1 Introduction 13
- Introduction 14
- 2 Processor Configuration 15
- 2.2 System Address Map 17
- 18 Datasheet, Volume 2 18
- 2.2.1 Legacy Address Range 19
- Datasheet, Volume 2 21 21
- 2.2.2.2 TSEG 22
- 2.2.2.5 Pre-allocated Memory 23
- 2.2.2.7 Intel 24
- Management Engine (Intel 24
- ME) UMA 24
- Datasheet, Volume 2 25 25
- 2.2.2.10 High BIOS Area 26
- Datasheet, Volume 2 27 27
- 2.2.3.1 Programming Model 28
- HOST/SYSTEM VIEW 29
- PHYSICAL MEMORY 29
- (DRAM CONTROLLER VIEW) 29
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.2.9 I/O Address Space 35
- 36 Datasheet, Volume 2 36
- Datasheet, Volume 2 37 37
- 2.4 Configuration Mechanisms 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 42 Datasheet, Volume 2 42
- Datasheet, Volume 2 43 43
- 2.6 I/O Mapped Registers 44
- 2.7.6 CC—Class Code Register 49
- TXT Lockable 54
- 1:0 to 11b 56
- 4) from 58
- B0h, bits 15:4) 58
- 2.8 MCHBAR Registers 66
- 00h RW 67
- Register Symbol Register Name 67
- 208–209h 73
- 20A–20Bh 74
- 24D–24Fh 74
- 250-251h 75
- 252–255h 76
- 256–257h 77
- 258–25Ah 77
- 269–26Eh 79
- 298–29Bh 82
- 29C–29Fh 84
- 2B4–2B7h 84
- 600–601h 86
- 602–603h 86
- 604–605h 86
- 64D–64Fh 88
- 650–651h 88
- 652–655h 89
- 656–657h 90
- 658–65Ah 90
- 660–663h 91
- 6B4–6B7h 93
- C20–C27h 94
- 1001–1002h 94
- 1004–1005h 95
- 101E–101Fh 100
- Register 107
- 10EC–10EDh 108
- 2C20–2C22h 109
- 2.9 EPBAR Registers 110
- 2.10 PCI Device 1 Registers 115
- PCI device 117
- Port Command Register 140
- 11:10 RW-O 11b 143
- OS's during run time 155
- 104–107h 156
- 108–10Bh 157
- 10C–10Dh 157
- 110–113h 158
- 23 RO 0b Reserved 158
- 114–117h 158
- 11A–11Bh 159
- 2.12 DMIBAR Registers 161
- Declaration Capability 169
- 2.13.6 CC—Class Code Register 177
- Range Address Register 179
- GMADR register 180
- 2.14 Device 2 I/O Registers 183
- 100–107h 211
- 108–10Fh 212
- 200–20Fh 214
- F00–F03h 215
- F04–F07h 216
- Dedication 217
- F08–F0Bh 218
- FFC–FFFh 219
- 2.16 DMI VC1 REMAP Registers 221
- 2.17.2 GFXPLL1—GFX PLL BIOS 254
- 2.18 GFXVTBAR Registers 255
- Address Register 281
- 2.19 PCI Device 6 Registers 288
- 2.19.45 RSTS—Root Status 327
- 2.21 Intel 332
- Specific Registers 332
- 110–117h 333
- 330–337h 333
- Lower Half Register 334
- Upper Half Register 334
- QuickPath Architecture 335
- System Address Decode 335
- Register Description 335
- QPI Link 0 Registers 340
- QPI Physical 0 Registers 341
- 3.4 PCI Standard Registers 342
- 3.4.4 CCR—Class Code Register 344
- Identification Register 345
- 3.4.7 PCICMD—Command Register 346
- 3.5.1 MAX_RTIDS 349
- 3.6.1 SAD_PAM0123 349
- 3.6.2 SAD_PAM456 351
- 3.6.3 SAD_HEN 352
- 3.6.4 SAD_SMRAM 353
- 3.6.5 SAD_PCIEXBAR 354
- 3.7 Intel 356
- QPI Link Registers 356
- 3.8 Intel 357
- QPI Physical Layer Registers 357
- 360 Datasheet, Volume 2 360
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Liebert Precision Cooling System DS podręczniki
Instrukcje obsługi i podręczniki użytkownika dla Sprzęt komputerowy Liebert Precision Cooling System DS.
Dostarczamy 1 pdf podręczników Liebert Precision Cooling System DS do pobrania za darmo według typów dokumentów: Instrukcja Użytkownika
Liebert Precision Cooling System DS Instrukcja Użytkownika (136 strony)
Marka: Liebert | Kategoria: Hardware | Rozmiar: 5.33 MB |
Spis treści
35"
22
33"
22
Approximate
23
DPN000924
24
TOP VIEW
26
FRONT VIEW
26
DPN001013
28
24"
33
Supply air
37
26"
39
Top of Unit
40
DPN001196
43
Piano Jacks
46
Forklift
46
DETAIL A
51
60-3/16"
57
(1529mm)
57
59-7/16"
60
(1509mm)
60
37"
61
31-1/4"
69
45-13/16"
71
(1163mm)
71
8.0 PIPING
82
INCORRECT
83
CUSTOMER
95
FRONT OF UNIT
101
Front View
101
Section A-A
101
DPN000803
101
Front of Unit
102
DPN000804
102
DPN000900
103
DPN000928
104
DPN000929
105
DPN000933
106
DPN001014
107
DPN001015
108
15-3/16"
109
DPN001119
110
15-7/8"
111
TOP VIEW OF UNIT
112
Top View
113
Front Of Unit
116
DPN001258
116
10.2 Electrical
117
10.3 Piping
117
10.4 Other
117
WARNING
118
12.0 MAINTENANCE
121
Maintenance
124
DPN000996
125
12.7 Compressor
127
Glycol Pump
134
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