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Datasheet, Volume 2 203

Processor Configuration Registers

2.15.15 PLMBASE_REG—Protected Low-Memory Base Register

This register is used to setup the base address of DMA protected low-memory region.

The register must be setup before enabling protected memory through PMEN_REG, and

must not be updated when protected memory regions are enabled. When

LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO). When

LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated RW).

This register is always treated as RO for implementations not supporting protected low

memory region (PLMR field reported as 0 in the Capability register). The alignment of

the protected low memory region base depends on the number of reserved bits (N) of

this register. Software may determine the value of N by writing all 1s to this register,

and finding most significant zero bit position with 0 in the value read back from the

B/D/F/Type: 0/0/0/VC0PREMAP

Address Offset: 68–6Bh

Reset Value: 00000000h

Access: RW, RO

Bit Attr

Reset

Value

Description

31:21 RW 000h Protected Low-Memory Base (PLMB)

This register specifies the base of size aligned, protected low-memory region

in system memory. The protected low-memory region has a minimum size of

2 MB and must be size aligned.

20:0 RO 000000h Reserved

1 2 ... 198 199 200 201 202 203 204 205 206 207 208 ... 359 360

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