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PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache

INTEGRATION TOOLS

Table 46. Debug Port Pinout Description and Requirements

Name Pin Description Specification Requirement Notes

Pentium® III Xeon™ processor

at 600 MHz+ .

GND 2, 4, 6,

13, 15,

17, 19,

21, 23,

25, 27

Signal ground. Connect all pins to signal

ground.

NOTES:

1. Resistor values with “~” preceding them can vary from the specified value; use resistor as close as possible to the value

specified.

2. Termination should include series (~240 ohm ) and AGTL+ termination (connected to 1.5V) resistors. Figure 30A.

3. Signal should be at end of daisy chain and the boundary scan chain should be partitioned into two distinct sections to

assist in debugging the system: one partition with only the processor(s) for system debug (i.e., used with the ITP) and

another with all other components for manufacturing or system test.

8.1.6 DEBUG PORT SIGNAL NOTES

In general, all open drain AGTL+ outputs from the system must be retained at a proper logic level, whether or

not the debug port is installed. RESET# from the processor system should be terminated at the debug port, as

shown Figure 30. R

should be a 150Ω on RESET#.

PRDYn# should have a similar layout, however R

should be 50Ω to match board impedance rather than the

normal 150Ω since there are only 2 loads on this signal.

Figure 30A. AGTL+ Signal Termination

8.1.6.1 General Signal Quality Notes

Signals from the debug port are fed to the system from the ITP via a buffer board and a cable. If system

signals routed to the debug port (i.e. TDO, PRDYn# and RESET#) are used elsewhere in the system, then

dedicated drivers should be used to isolate the signals from reflections coming from the end of this cable. If

the Pentium® III Xeon™ processor at 600 MHz+ boundary scan signals are used elsewhere in the system,

then the TDI, TMS, TCK, and TRST# signals from the debug port should be isolated from the system signals.

In general, no signals should be left floating. Thus, signals going from the debug port to the processor system

should not be left floating. If they are left floating, there may be problems when the ITP is not plugged into the

connector.

8.1.6.2 Signal Note: DBRESET#

1 2 ... 73 74 75 76 77 78 79 80 81 82 83 ... 102 103

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Summit FRBW52D Handbuch (31 Seiten)

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Inhaltsverzeichnis

FELIX STORCH, INC

770 Garrison Avenue

Bronx, New York 10474

Table of Contents

Description of Models

IMPORTANT SAFEGUARDS

- SAVE THESE INSTRUCTIONS

INSTALLATION

OPERATION

The Upper Warming Cabinet

CLEANING AND MAINTENANCE

WIRING DIAGRAM

TROUBLESHOOTING

LIMITED WARRANTY

Introduction

Table des matières

Description des Modèles

Installation

Fonctionnement

Nettoyage et entretien

Filtre à peluches

Temps d'arrêt prolongé

Entretien préventif

MODÈLES :

Dépannage

Notes

Garantie limitée

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