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PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache

ELECTRICAL SPECIFICATIONS

TCK

TDI, TMS

Input

Signals

TDO

Output

Signals

P6CB766a

1.25V

T43 (All Non-Test Inputs Setup Time)=

T44 (All Non-Test Inputs Hold Time)=

T40 (TDO Float Delay)=

T37 (TDI, TMS Setup Time)=

T38 (TDI, TMS Hold Time)=

T39 (TDO Valid Delay)=

T41 (All Non-Test Outputs Valid Delay)=

T42 (All Non-Test Outputs Float Delay)=

Non-Test

Figure 9. Test Timings (Boundary Scan)

TRST#

P6CB-

1.25V

T36 (TRST# Pulse Width)=

Figure 10. Test Reset Timings

1 2 ... 25 26 27 28 29 30 31 32 33 34 35 ... 102 103

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