Intel RH80532NC033256 Ficha Técnica descarregar pdf (Página 51)

Mobile Intel

Celeron

Processor (0.13 µ)

Micro-FCBGA and Micro-FCPGA Packages Datasheet

298517-006 Datasheet 51

Figure 13. Setup and Hold Timings

Si gnal

VValid

D0005-0

NOTES:

= T8, T27 (Setup Time)

= T9, T28 (Hold Time)

V = V

REF

for AGTL signals; 1.0V for CMOS, APIC, and TAP signals

Vc = Crossing point of BCLK rising edge and BCLK# falling edge for BCLK references (Differential Clock)

= 1.25V (Single Ended Clock)

Figure 14. Cold/Warm Reset and Configuration Timings

BCLK

RESET#

D0006-02

Configuration

(A[15:5], BREQ0#,

FLUSH#, INIT#,

PICD0)

Valid

PICD[1:0]

AGTL/non-AGTL

outputs

Non-configuration

inputs

Valid

Active

NOTES:

= T9 (AGTL Input Hold Time)

= T8 (AGTL Input Setup Time)

= T10 (RESET# Pulse Width)

= T16 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Setup Time)

= T17 (Reset Configuration Signals (A[15:5]#, BREQ0#, FLUSH#, INIT#, PICD0) Hold Time)

Ty = T18D (RESET# inactive to Valid Outputs)

Tz = T18E (RESET# inactive to Drive Signals)

Vc= Crossing point of BCLK rising edge and BCLK# falling edge (Differential Clock)

= 1.25 V (Single Ended Clock)

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