Intel E3-1275 Ficha Técnica descarregar pdf (Página 84)

100

101

Processor Configuration Registers

84 Datasheet, Volume 2

7:4 RO-FW 0h Reserved

3:3 RO 0h Reserved

2:0 RO-FW 000b Uncore

DDR3 Maximum Frequency Capability (DMFC)

This field controls which values may be written to the Memory

Frequency Select field 6:4 of the Clocking Configuration

registers (MCHBAR Offset C00h). Any attempt to write an

unsupported value will be ignored.

000 = MC capable of "All" memory frequencies

101 = Reserved

110 = MC capable of up to DDR3 1333

111 = MC capable of up to DDR3 1067

B/D/F/Type: 0/0/0/PCI

Address Offset: E4–E7h

Default Value: 0000_0000h

Access: RO-FW, RO-KFW

Size: 32 bits

BIOS Optimal Default: 000000h

Bit Attr

Reset

Value

RST/

PWR

Description

1 2 ... 79 80 81 82 83 84 85 86 87 88 89 ... 299 300

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