Intel E3-1275 Ficha Técnica descarregar pdf (Página 190)

Processor Configuration Registers

190 Datasheet, Volume 2

2.12.2 DMIPVCCAP1—DMI Port VC Capability Register 1

This register describes the configuration of PCI Express Virtual Channels associated

with this port.

2.12.3 DMIPVCCAP2—DMI Port VC Capability Register 2

This register describes the configuration of PCI Express Virtual Channels associated

with this port.

B/D/F/Type: 0/0/0/DMIBAR

Address Offset: 4–7h

Reset Value: 0000_0000h

Access: RO, RW-O

Size: 32 bits

BIOS Optimal Default 0000000h

Bit Attr

Reset

Value

RST/

PWR

Description

31:7 RO 0h Reserved

6:4 RO 000b Uncore

Low Priority Extended VC Count (LPEVCC)

This field indicates the number of (extended) Virtual Channels in

addition to the default VC belonging to the low-priority VC (LPVC)

group that has the lowest priority with respect to other VC

resources in a strict-priority VC Arbitration.

The value of 0 in this field implies strict VC arbitration.

3 RO 0h Reserved

2:0 RW-O 000b Uncore

Extended VC Count (EVCC)

This field indicates the number of (extended) Virtual Channels in

addition to the default VC supported by the device.

B/D/F/Type: 0/0/0/DMIBAR

Address Offset: 8–Bh

Reset Value: 0000_0000h

Access: RO

Size: 32 bits

BIOS Optimal Default 0000h

Bit Attr

Reset

Value

RST/

PWR

Description

31:24 RO 00h Uncore Reserved for VC Arbitration Table Offset (VCATO)

23:8 RO 0h Reserved

7:0 RO 00h Uncore Reserved for VC Arbitration Capability (VCAC)

1 2 ... 185 186 187 188 189 190 191 192 193 194 195 ... 299 300

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