Intel CM8063701391600 Ficha Técnica descarregar pdf (Página 33)

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Datasheet, Volume 1 33

Interfaces

2.5 Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between

processor and a PECI master, usually the PCH. The processor implements a PECI

interface to:

• Allow communication of processor thermal and other information to the PECI

master.

• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.

2.6 Interface Clocking

2.6.1 Internal Clocking Requirements

§ §

Table 2-4. Processor Reference Clock Requirements

Reference Input Clocks Input Frequency Associated PLL

BCLK[0]/BCLK#[0] 133 MHz Processor/Memory

PEG_CLK/PEG_CLK# 100 MHz PCI Express/DMI/Intel FDI

1 2 ... 28 29 30 31 32 33 34 35 36 37 38 ... 101 102

Datasheet – Volume 1 1
2 Datasheet, Volume 1 2
Contents 3
4 Datasheet, Volume 1 4
Datasheet, Volume 1 5 5
6 Datasheet, Volume 1 6
Revision History 7
8 Datasheet, Volume 1 8
1 Introduction 9
Figure 1-1. Intel 10
Pentium 10
1.1 Processor Feature Details 11
1.2 Interfaces 11
1.2.2 PCI Express* 12
Datasheet, Volume 1 13 13
Introduction 13
1.5 Package 15
1.6 Terminology 15
1.3 Power Management Support 15
1.7 Related Documents 18
2 Interfaces 19
Interfaces 20
2.1.3.1 Single-Channel Mode 21
Flex Memory Technology Mode 21
2.1.5.2 Command Overlap 23
2.2 PCI Express* Interface 24
2.2.1.1 Transaction Layer 25
2.2.1.2 Data Link Layer 25
2.2.1.3 Physical Layer 25
2.2.3 PCI Express Port 26
2.4 Integrated Graphics 27
2.4.1.2 3D Pipeline 28
2.4.1.3 Video Engine 29
2.4.1.4 2D Engine 29
2.4.2.1 Display Planes 31
2.4.2.2 Display Pipes 32
2.4.2.3 Display Ports 32
2.6 Interface Clocking 33
3 Technologies 35
3.1.3 Intel 36
VT-d Objectives 36
3.1.4 Intel 36
VT-d Features 36
3.2 Intel 37
3.3 Intel 38
Hyper-Threading Technology 38
3.4 Intel 38
Turbo Boost Technology 38
3.5 New Instructions 38
4 Power Management 39
4.2.1 Enhanced Intel 41
SpeedStep 41
Technology 41
4.2.2 Low-Power Idle States 41
C1 C1 E C6C3 42
4.2.4.1 Core C0 State 44
4.2.4.2 Core C1/C1E State 44
4.2.4.3 Core C3 State 44
4.2.4.4 Core C6 State 44
4.2.4.5 C-State Auto-Demotion 45
4.2.5.1 Package C0 46
4.2.5.2 Package C1/C1E 47
4.2.5.3 Package C3 State 47
4.2.5.4 Package C6 State 47
Management 48
4.5.1 Graphics Render C-State 50
5 Thermal Management 51
Thermal Management 52
6 Signal Description 53
6.1 System Memory Interface 54
Table 6-3. Memory Channel B 55
Signal Description 56
6.6 PLL Signals 58
6.7 Intel 59
6.8 JTAG/ITP Signals 59
6.10 Power Sequencing 61
6.13 Ground and NCTF 63
7 Electrical Specifications 65
Voltage Identification (VID) 66
Electrical Specifications 68
7.7 Signal Groups 70
7.10 DC Specifications 74
(Sheet 2 of 2) 75
Specifications 76
Table 7-8. V 76
Figure 7-1. V 77
Table 7-9. V 78
Figure 7-2. V 78
DC Specifications 82
Datasheet, Volume 1 83 83
8 Processor Land and Signal 85
86 Datasheet, Volume 1 86
Datasheet, Volume 1 87 87
88 Datasheet, Volume 1 88

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