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Intel
®
Xeon
®
Processor E5-1600/E5-2600/E5-4600 v2 Product Families 199
Datasheet Volume One of Two
Processor Land Listing
CM38 VSS GND
CM4 DDR1_DQ[04] SSTL I/O
CM40 VSS GND
CM42 VSS GND
CM44 BCLK0_DN CMOS I
CM46 QPI1_DRX_DN[18] QPI I
CM48 QPI1_DRX_DN[16] QPI I
CM50 QPI1_DRX_DP[14] QPI I
CM52 QPI1_DRX_DN[10] QPI I
CM54 QPI1_DRX_DN[05] QPI I
CM56 QPI1_DRX_DN[04] QPI I
CM6 VSS GND
CM8 VSS GND
CN11 VSS GND
CN13 VSS GND
CN15 VSS GND
CN17 VSS GND
CN19 DDR0_MA[15] SSTL O
CN21 DDR0_MA[09] SSTL O
CN23 DDR0_MA[06] SSTL O
CN25 DDR0_CS_N[0] SSTL O
CN27 DDR0_BA[1] SSTL O
CN29 DDR0_WE_N SSTL O
CN3 VSS GND
CN31 VSS GND
CN33 VSS GND
CN35 VSS GND
CN37 VSS GND
CN39 VSS GND
CN41 DDR_VREFDQTX_C01 DC O
CN43 BCLK0_DP CMOS I
CN45 QPI1_DRX_DN[19] QPI I
CN47 QPI1_DRX_DN[17] QPI I
CN49 QPI1_DRX_DP[15] QPI I
CN5 VSS GND
CN51 QPI1_DRX_DP[13] QPI I
CN53 VSS GND
CN55 VSS GND
CN57 VSS GND
CN7 VSS GND
CN9 VSS GND
CP10 DDR1_DQ[19] SSTL I/O
Table 8-2. Land Number (Sheet 29 of 49)
Land No. Land Name Buffer Type Direction
CP12 VSS GND
CP14 DDR1_DQS_DN[12] SSTL I/O
CP16 VSS GND
CP18 DDR0_CKE[3] SSTL O
CP2 DDR1_DQ[01] SSTL I/O
CP20 VCCD_01 PWR
CP22 VCCD_01 PWR
CP24 VCCD_01 PWR
CP26 VCCD_01 PWR
CP28 VCCD_01 PWR
CP30 DDR1_DQ[33] SSTL I/O
CP32 DDR1_DQS_DP[04] SSTL I/O
CP34 DDR1_DQ[35] SSTL I/O
CP36 VSS GND
CP38 DDR1_DQS_DP[15] SSTL I/O
CP4 DDR1_DQ[00] SSTL I/O
CP40 VSS GND
CP42 VSS GND
CP44 VSS GND
CP46 VSS GND
CP48 VSS GND
CP50 VSS GND
CP52 VSS GND
CP54 RSVD
CP56 VSS GND
CP58 QPI1_DRX_DP[06] QPI I
CP6 DDR1_DQ[20] SSTL I/O
CP8 DDR1_DQS_DP[11] SSTL I/O
CR1 DDR1_DQS_DN[09] SSTL I/O
CR11 VSS GND
CR13 DDR1_DQ[24] SSTL I/O
CR15 DDR1_DQS_DN[03] SSTL I/O
CR17 DDR1_DQ[26] SSTL I/O
CR19 DDR1_CKE[4] SSTL O
CR21 DDR1_CS_N[8] SSTL O
CR23 DDR1_CS_N[2] SSTL O
CR25 DDR0_MA[01] SSTL O
CR27 DDR1_CS_N[3] SSTL O
CR29 DDR1_DQ[37] SSTL I/O
CR3 DDR1_DQS_DP[00] SSTL I/O
CR31 DDR1_DQS_DN[13] SSTL I/O
CR33 DDR1_DQ[39] SSTL I/O
Table 8-2. Land Number (Sheet 30 of 49)
Land No. Land Name Buffer Type Direction
- Processor E5-1600/E5 1
- Table of Contents 3
- Revision History 10
- 1 Overview 11
- Processor 13
- 1.1.2 Supported Technologies 15
- 1.2 Interfaces 16
- 1.2.2 PCI Express* 17
- Transaction 18
- 1.2.4 Intel 19
- 1.3 Power Management Support 20
- 1.5 Package Summary 21
- 1.6 Terminology 21
- 1.7 Related Documents 24
- 1.9 State of Data 24
- 2 Interfaces 25
- 2.2 PCI Express* Interface 26
- 2.2.1.1 Transaction Layer 27
- 2.2.1.2 Data Link Layer 27
- 2.2.1.3 Physical Layer 27
- 2.3.1 DMI2 Error Flow 28
- 2.3.3 DMI2 Link Down 28
- Datasheet Volume One of Two 29
- Interfaces 29
- 2.5.1.1 Thermal Management 30
- 2.5.2 Client Command Suite 31
- Reserved 32
- # of Domains 32
- Byte# 5 32
- Major Revision# 33
- Minor Revision# 33
- Byte# 6 33
- 2.5.2.4 RdPkgConfig() 34
- 2.5.2.5 WrPkgConfig() 36
- Channel Temperature Data 43
- 816232431 43
- DRAM Power Limit Performance 45
- CPU ID Data 49
- CPU code patch revision 50
- RESERVED 55
- Current Config Limit Data 55
- Accumulated Energy Status 56
- Accumulated CPU Energy 56
- Accumulated CPU Throttle Time 58
- 2.5.2.7 RdIAMSR() 60
- 2.5.2.8 RdPCIConfig() 64
- 2.5.2.9 RdPCIConfigLocal() 65
- DeviceBus Function Register 66
- 2.5.2.10 WrPCIConfigLocal() 67
- 2.5.3.1 Power-up Sequencing 69
- 2.5.3.2 Device Discovery 70
- 2.5.3.3 Client Addressing 70
- 2.5.3.4 C-states 71
- 2.5.3.5 S-states 72
- 2.5.3.6 Processor Reset 72
- 2.5.4 Multi-Domain Commands 74
- 2.5.5.1 Abort FCS 75
- 2.5.5.2 Completion Codes 75
- 2.5.7.1 Format 76
- 2.5.7.2 Interpretation 76
- 3 Technologies 79
- 3.1.2 Intel 80
- VT-x Features 80
- 3.1.3 Intel® VT-d Objectives 80
- 3.2 Security Technologies 81
- 3.2.3 AES Instructions 82
- 3.3 Intel 83
- Secure Key 83
- 3.4 Intel 83
- OS Guard 83
- 3.6 Intel 84
- Turbo Boost Technology 84
- 3.10 Intel 86
- Dynamic Power Technology 86
- 4 Power Management 87
- Table 4-6. Intel® QPI States 89
- 4.2.2 Low-Power Idle States 90
- C1 C1E C6C3 91
- 4.2.4.1 Core C0 State 92
- 4.2.4.2 Core C1/C1E State 92
- 4.2.4.3 Core C3 State 93
- 4.2.4.4 Core C6 State 93
- 4.2.4.5 Delayed Deep C-States 93
- 4.2.5.1 Package C0 95
- 4.2.5.2 Package C1/C1E 95
- 4.2.5.3 Package C2 State 96
- 4.2.5.4 Package C3 State 96
- 4.2.5.5 Package C6 State 96
- 4.3.1 CKE Power-Down 98
- 4.3.2.1 Self Refresh Entry 99
- 4.3.2.2 Self Refresh Exit 99
- 4.3.2.3 DLL and PLL Shutdown 99
- 5 Thermal Management 101
- CASE_MAX_B 102
- CC activation 103
- Table 5-1. T 105
- 5.1.5 Thermal Metrology 111
- 5.2.1 Processor Temperature 112
- Intel® Xeon® Processor E5 113
- Design Guide 113
- 5.2.2.2 Clock Modulation 115
- 5.2.4 PROCHOT_N Signal 116
- 5.2.5 THERMTRIP_N Signal 116
- Interface 118
- 6 Signal Descriptions 119
- 6.5 PECI Signal 123
- 6.7 JTAG and TAP Signals 123
- Miscellaneous Signals 124
- 7 Electrical Specifications 129
- BCLK{0/1}_DN) 130
- 7.1.6.1 PLL Power Supply 131
- 7.1.9.2 Decoupling Guidelines 132
- contains further 133
- Table 7-2. SVID Address Usage 135
- 7.2 Signal Group Summary 136
- 7.5 Mixing Processors 141
- 7.8 DC Specifications 143
- Table 7-13. Processor V 146
- Figure 7-3. Processor V 147
- 7.8.2.1 V 148
- Overshoot Specifications 148
- Time [us] 149
- Unit Figure Notes 151
- VHavg (mV) 155
- 250 + 0.5 (VHavg - 700) 155
- 550 + 0.5 (VHavg - 700) 155
- 7.9 Signal Quality 156
- 7.9.5.3 Activity Factor 157
- Specifications 158
- 1.3335 V 0.2835 V 3 ns 5 ns 159
- 1.2600 V 0.210 V 5 ns 5 ns 159
- 8 Processor Land Listing 161
- 8.2 Listing by Land Number 185
- 9 Package Mechanical 211
- Intel® Xeon® 217
- 9.8 Processor Materials 218
- 9.9 Processor Markings 218
- 10.1 Introduction 219
- Keepout Zones 221
- LEGEND, SHEETS 1 & 2 ONLY 222
- AS VIEWED FROM PRIMARY 223
- SIDE OF MAINBOARD 223
- AS VIEWED FROM SECONDARY 224
- LEGEND, SHEET 3 ONLY 224
- BG11950D 225
- Bases Only 226
- BE95132D 227
- Support (ILM-RS) 230
- °C. Meeting the 231
- (Blade + 1U + 2U Rack) 232
- 10.4 Boxed Processor Contents 234
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