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Intel
®
Xeon
®
Processor E5-1600/E5-2600/E5-4600 v2 Product Families 187
Datasheet Volume One of Two
Processor Land Listing
AE31 VSS GND
AE33 DDR2_DQ[26] SSTL I/O
AE35 DDR2_DQ[25] SSTL I/O
AE37 DDR2_DQ[15] SSTL I/O
AE39 VSS GND
AE41 DDR2_DQ[08] SSTL I/O
AE43 VSS GND
AE45 VTTA PWR
AE47 VSS GND
AE49 VSS GND
AE5 DDR2_DQ[59] SSTL I/O
AE51 VSS GND
AE53 VTTA PWR
AE55 PE2B_RX_DN[6] PCIEX3 I
AE57 PE2B_RX_DP[7] PCIEX3 I
AE7 DDR2_DQ[47] SSTL I/O
AE9 VSS GND
AF10 DDR2_DQ[35] SSTL I/O
AF12 VSS GND
AF14 VSS_VSA_SENSE O
AF16 VSS GND
AF18 VSA PWR
AF2 DDR2_DQ[62] SSTL I/O
AF20 VSS GND
AF22 VTTD PWR
AF24 VTTD PWR
AF26 VSS GND
AF28 DDR2_ECC[1] SSTL I/O
AF30 DDR2_ECC[0] SSTL I/O
AF32 DDR2_DQ[27] SSTL I/O
AF34 VSS GND
AF36 VSS GND
AF38 DDR2_DQ[14] SSTL I/O
AF4 DDR2_DQ[58] SSTL I/O
AF40 VSS GND
AF42 VSS GND
AF44 PE3A_RX_DP[0] PCIEX3 I
AF46 PE3A_RX_DP[2] PCIEX3 I
AF48 PE3C_RX_DP[8] PCIEX3 I
AF50 PE3C_RX_DP[10] PCIEX3 I
AF52 PE_RBIAS_SENSE PCIEX3 I
AF54 VSS GND
Table 8-2. Land Number (Sheet 5 of 49)
Land No. Land Name Buffer Type Direction
AF56 VSS GND
AF58 PE2B_RX_DN[7] PCIEX3 I
AF6 VSS GND
AF8 DDR2_DQ[42] SSTL I/O
AG1 VSS GND
AG11 DDR2_DQ[34] SSTL I/O
AG13 VSA_SENSE O
AG15 VSA PWR
AG17 VSA PWR
AG19 VCC PWR
AG21 VTTD PWR
AG23 VTTD PWR
AG25 VCC PWR
AG27 VCC PWR
AG29 VCC PWR
AG3 VSS GND
AG31 VCC PWR
AG33 VCC PWR
AG35 VCC PWR
AG37 VCC PWR
AG39 VCC PWR
AG41 VCC PWR
AG43 VSS GND
AG45 PE3A_RX_DP[1] PCIEX3 I
AG47 PE3D_RX_DP[12] PCIEX3 I
AG49 PE3C_RX_DP[11] PCIEX3 I
AG5 VSS GND
AG51 PE3C_RX_DP[9] PCIEX3 I
AG53 PE2B_TX_DP[4] PCIEX3 O
AG55 VSS GND
AG57 VSS GND
AG7 DDR2_DQ[43] SSTL I/O
AG9 VSS GND
AH10 VSA PWR
AH12 VSA PWR
AH14 VSA PWR
AH16 VSA PWR
AH2 VSA PWR
AH4 VSA PWR
AH42 IVT_ID_N O
AH44 PE3A_RX_DN[0] PCIEX3 I
AH46 PE3A_RX_DN[2] PCIEX3 I
Table 8-2. Land Number (Sheet 6 of 49)
Land No. Land Name Buffer Type Direction
- Processor E5-1600/E5 1
- Table of Contents 3
- Revision History 10
- 1 Overview 11
- Processor 13
- 1.1.2 Supported Technologies 15
- 1.2 Interfaces 16
- 1.2.2 PCI Express* 17
- Transaction 18
- 1.2.4 Intel 19
- 1.3 Power Management Support 20
- 1.5 Package Summary 21
- 1.6 Terminology 21
- 1.7 Related Documents 24
- 1.9 State of Data 24
- 2 Interfaces 25
- 2.2 PCI Express* Interface 26
- 2.2.1.1 Transaction Layer 27
- 2.2.1.2 Data Link Layer 27
- 2.2.1.3 Physical Layer 27
- 2.3.1 DMI2 Error Flow 28
- 2.3.3 DMI2 Link Down 28
- Datasheet Volume One of Two 29
- Interfaces 29
- 2.5.1.1 Thermal Management 30
- 2.5.2 Client Command Suite 31
- Reserved 32
- # of Domains 32
- Byte# 5 32
- Major Revision# 33
- Minor Revision# 33
- Byte# 6 33
- 2.5.2.4 RdPkgConfig() 34
- 2.5.2.5 WrPkgConfig() 36
- Channel Temperature Data 43
- 816232431 43
- DRAM Power Limit Performance 45
- CPU ID Data 49
- CPU code patch revision 50
- RESERVED 55
- Current Config Limit Data 55
- Accumulated Energy Status 56
- Accumulated CPU Energy 56
- Accumulated CPU Throttle Time 58
- 2.5.2.7 RdIAMSR() 60
- 2.5.2.8 RdPCIConfig() 64
- 2.5.2.9 RdPCIConfigLocal() 65
- DeviceBus Function Register 66
- 2.5.2.10 WrPCIConfigLocal() 67
- 2.5.3.1 Power-up Sequencing 69
- 2.5.3.2 Device Discovery 70
- 2.5.3.3 Client Addressing 70
- 2.5.3.4 C-states 71
- 2.5.3.5 S-states 72
- 2.5.3.6 Processor Reset 72
- 2.5.4 Multi-Domain Commands 74
- 2.5.5.1 Abort FCS 75
- 2.5.5.2 Completion Codes 75
- 2.5.7.1 Format 76
- 2.5.7.2 Interpretation 76
- 3 Technologies 79
- 3.1.2 Intel 80
- VT-x Features 80
- 3.1.3 Intel® VT-d Objectives 80
- 3.2 Security Technologies 81
- 3.2.3 AES Instructions 82
- 3.3 Intel 83
- Secure Key 83
- 3.4 Intel 83
- OS Guard 83
- 3.6 Intel 84
- Turbo Boost Technology 84
- 3.10 Intel 86
- Dynamic Power Technology 86
- 4 Power Management 87
- Table 4-6. Intel® QPI States 89
- 4.2.2 Low-Power Idle States 90
- C1 C1E C6C3 91
- 4.2.4.1 Core C0 State 92
- 4.2.4.2 Core C1/C1E State 92
- 4.2.4.3 Core C3 State 93
- 4.2.4.4 Core C6 State 93
- 4.2.4.5 Delayed Deep C-States 93
- 4.2.5.1 Package C0 95
- 4.2.5.2 Package C1/C1E 95
- 4.2.5.3 Package C2 State 96
- 4.2.5.4 Package C3 State 96
- 4.2.5.5 Package C6 State 96
- 4.3.1 CKE Power-Down 98
- 4.3.2.1 Self Refresh Entry 99
- 4.3.2.2 Self Refresh Exit 99
- 4.3.2.3 DLL and PLL Shutdown 99
- 5 Thermal Management 101
- CASE_MAX_B 102
- CC activation 103
- Table 5-1. T 105
- 5.1.5 Thermal Metrology 111
- 5.2.1 Processor Temperature 112
- Intel® Xeon® Processor E5 113
- Design Guide 113
- 5.2.2.2 Clock Modulation 115
- 5.2.4 PROCHOT_N Signal 116
- 5.2.5 THERMTRIP_N Signal 116
- Interface 118
- 6 Signal Descriptions 119
- 6.5 PECI Signal 123
- 6.7 JTAG and TAP Signals 123
- Miscellaneous Signals 124
- 7 Electrical Specifications 129
- BCLK{0/1}_DN) 130
- 7.1.6.1 PLL Power Supply 131
- 7.1.9.2 Decoupling Guidelines 132
- contains further 133
- Table 7-2. SVID Address Usage 135
- 7.2 Signal Group Summary 136
- 7.5 Mixing Processors 141
- 7.8 DC Specifications 143
- Table 7-13. Processor V 146
- Figure 7-3. Processor V 147
- 7.8.2.1 V 148
- Overshoot Specifications 148
- Time [us] 149
- Unit Figure Notes 151
- VHavg (mV) 155
- 250 + 0.5 (VHavg - 700) 155
- 550 + 0.5 (VHavg - 700) 155
- 7.9 Signal Quality 156
- 7.9.5.3 Activity Factor 157
- Specifications 158
- 1.3335 V 0.2835 V 3 ns 5 ns 159
- 1.2600 V 0.210 V 5 ns 5 ns 159
- 8 Processor Land Listing 161
- 8.2 Listing by Land Number 185
- 9 Package Mechanical 211
- Intel® Xeon® 217
- 9.8 Processor Materials 218
- 9.9 Processor Markings 218
- 10.1 Introduction 219
- Keepout Zones 221
- LEGEND, SHEETS 1 & 2 ONLY 222
- AS VIEWED FROM PRIMARY 223
- SIDE OF MAINBOARD 223
- AS VIEWED FROM SECONDARY 224
- LEGEND, SHEET 3 ONLY 224
- BG11950D 225
- Bases Only 226
- BE95132D 227
- Support (ILM-RS) 230
- °C. Meeting the 231
- (Blade + 1U + 2U Rack) 232
- 10.4 Boxed Processor Contents 234
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