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Intel® Celeron® Mobile Processor Dual-Core on 45-nm Process DatasheetFor Platforms Based on Mobile Intel® 4 Series Express Chipset FamilySeptember 200

Introduction10 Datasheet

Datasheet 11Low Power Features2 Low Power Features2.1 Clock Control and Low Power StatesThe processor supports the C1/AutoHALT, C1/MWAIT, C2, C3 and s

Low Power Features12 Datasheet 2.1.1 Core Low-Power States2.1.1.1 C0 StateThis is the normal operating state of the processor.2.1.1.2 C1/AutoHALT Powe

Datasheet 13Low Power Features2.1.1.3 C1/MWAIT Powerdown StateC1/MWAIT is a low-power state entered when the processor core executes the MWAIT instruc

Low Power Features14 DatasheetSince the AGTL+ signal pins receive power from the FSB, these pins should not be driven (allowing the level to return to

Datasheet 15Low Power Features2.1.2.5 Deep Sleep StateDeep Sleep state is a very low-power state the processor can enter while maintaining context. De

Low Power Features16 Datasheet• The processor controls voltage ramp rates internally to ensure glitch-free transitions.• Low transition latency and la

Datasheet 17Low Power Features2.4 Processor Power Status Indicator (PSI#) SignalThe PSI# signal is asserted when the processor is in a reduced power c

Low Power Features18 Datasheet

Datasheet 19Electrical Specifications3 Electrical Specifications3.1 Power and Ground PinsFor clean, on-chip power distribution, the processor has a la

2 DatasheetLegal Lines and DisclaimersINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

Electrical Specifications20 Datasheet0 0 1 0 1 1 0 1.22500 0 1 0 1 1 1 1.21250 0 1 1 0 0 0 1.20000 0 1 1 0 0 1 1.18750 0 1 1 0 1 0 1.17500 0 1 1 0 1 1

Datasheet 21Electrical Specifications1 0 0 0 1 0 1 0.63751 0 0 0 1 1 0 0.62501 0 0 0 1 1 1 0.61251 0 0 1 0 0 0 0.60001 0 0 1 0 0 1 0.58751 0 0 1 0 1 0

Electrical Specifications22 Datasheet3.4 Catastrophic Thermal ProtectionThe processor supports the THERMTRIP# signal for catastrophic thermal protecti

Datasheet 23Electrical Specifications3.6 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the proces

Electrical Specifications24 DatasheetNOTES:1. Refer to Chapter 4 for signal descriptions and termination requirements.2. In processor systems where th

Datasheet 25Electrical Specifications3.8 CMOS SignalsCMOS input signals are shown in Tabl e 4 . Legacy output FERR#, IERR# and other non-AGTL+ signals

Electrical Specifications26 Datasheet3.10 Processor DC SpecificationsThe processor DC specifications in this section are defined at the processor core

Datasheet 27Electrical SpecificationsNOTES:1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at ma

Electrical Specifications28 DatasheetNOTES:1. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at ma

Datasheet 29Electrical SpecificationsTable 8 lists the DC specifications for the processor and are valid only while meeting specifications for junctio

Datasheet 3Contents1Introduction...71.1 Ter

Electrical Specifications30 Datasheet5. 800-MHz FSB supported6. Measured at the bulk capacitors on the motherboard.7. Based on simulations and average

Datasheet 31Electrical SpecificationsNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. VIL is de

Electrical Specifications32 DatasheetNOTES:1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.2. The VCCP

Datasheet 33Package Mechanical Specifications and Pin Information4 Package Mechanical Specifications and Pin Information4.1 Package Mechanical Specifi

Package Mechanical Specifications and Pin Information34 DatasheetFigure 3. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2) h

Datasheet 35Package Mechanical Specifications and Pin InformationFigure 4. 4-MB and Fused 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)

Package Mechanical Specifications and Pin Information36 DatasheetFigure 5. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 1 of 2)

Datasheet 37Package Mechanical Specifications and Pin InformationFigure 6. 2-MB Micro-FCPGA Processor Package Drawing (Sheet 2 of 2)

Package Mechanical Specifications and Pin Information38 DatasheetFigure 7. SFF (ULV DC) Die Micro-FCBGA Processor Package Drawingø0.14AABLCø0.04ø0.46±

Datasheet 39Package Mechanical Specifications and Pin Information4.2 Processor Pinout and Pin ListTa b le 1 3 shows the top view pinout of the Intel

4 DatasheetFigures1 Package-Level Low-Power States ...112 Core Low-Power

Package Mechanical Specifications and Pin Information40 DatasheetTable 14. The Coordinates of the Processor Pins as Viewed from the Top of the Package

Datasheet 41Package Mechanical Specifications and Pin InformationTable 15. SFF Processor Top View Upper Left SideBD BC BB BA AY AW AV AU AT AR AP AN A

Package Mechanical Specifications and Pin Information42 DatasheetTable 16. SFF Processor Top View Upper Right SideAB AA Y W V U T R P N M L K J H G F

Datasheet 43Package Mechanical Specifications and Pin InformationTable 17. SFF Processor Top View Lower Left SideBD BC BB BA AY AW AV AU AT AR AP AN A

Package Mechanical Specifications and Pin Information44 DatasheetTable 18. SFF Processor Top View Lower Right SideAB AA Y W V U T R P N M L K J H G F

Datasheet 45Package Mechanical Specifications and Pin InformationTable 19. Pin Listing by Pin Name (Sheet 1 of 16)Pin NamePin NumberSignal Buffer T

Package Mechanical Specifications and Pin Information46 DatasheetBR0# F1 Common ClockInput/OutputBSEL[0] B22 CMOS OutputBSEL[1] B23 CMOS OutputBSEL[

Datasheet 47Package Mechanical Specifications and Pin InformationD[37]# T22 Source SynchInput/OutputD[38]# U25 Source SynchInput/OutputD[39]# U23 So

Package Mechanical Specifications and Pin Information48 DatasheetDSTBP[3]# AF24 Source SynchInput/OutputFERR# A5 Open Drain OutputGTLREF AD26 Power/

Datasheet 49Package Mechanical Specifications and Pin InformationVCC AA13 Power/OtherVCC AA15 Power/OtherVCC AA17 Power/OtherVCC AA18 Power/OtherVCC

Datasheet 5Revision History§Document NumberRevision NumberDescription Date321111 -001 • Initial Release November 2008321111 -002 • Added T3000, T3100,

Package Mechanical Specifications and Pin Information50 DatasheetVCC E12 Power/OtherVCC E13 Power/OtherVCC E15 Power/OtherVCC E17 Power/OtherVCC E18

Datasheet 51Package Mechanical Specifications and Pin InformationVSS AC14 Power/OtherVSS AC16 Power/OtherVSS AC19 Power/OtherVSS AC21 Power/OtherVSS

Package Mechanical Specifications and Pin Information52 DatasheetVSS F16 Power/OtherVSS F19 Power/OtherVSS F22 Power/OtherVSS F25 Power/OtherVSS G1

Datasheet 53Package Mechanical Specifications and Pin InformationVSS A8 Power/OtherVCC A9 Power/OtherVCC A10 Power/OtherVSS A11 Power/OtherVCC A12 P

Package Mechanical Specifications and Pin Information54 DatasheetD[51]# AB22 Source SynchInput/OutputVSS AB23 Power/OtherD[33]# AB24 Source SynchInp

Datasheet 55Package Mechanical Specifications and Pin InformationVID[2] AE5 CMOS OutputPSI# AE6 CMOS OutputVSSSENSE AE7 Power/Other OutputVSS AE8 Po

Package Mechanical Specifications and Pin Information56 DatasheetBSEL[0] B22 CMOS OutputBSEL[1] B23 CMOS OutputVSS B24 Power/OtherTHRMDC B25 Power/O

Datasheet 57Package Mechanical Specifications and Pin InformationVCC E12 Power/OtherVCC E13 Power/OtherVSS E14 Power/OtherVCC E15 Power/OtherVSS E16

Package Mechanical Specifications and Pin Information58 DatasheetVSS H6 Power/OtherVSS H21 Power/OtherD[12]# H22 Source SynchInput/OutputD[15]# H23

Datasheet 59Package Mechanical Specifications and Pin InformationDSTBP[1]# M26 Source SynchInput/OutputVSS N1 Power/OtherA[8]# N2 Source SynchInput/

6 Datasheet

Package Mechanical Specifications and Pin Information60 DatasheetA[18]# U5 Source SynchInput/OutputVSS U6 Power/OtherVSS U21 Power/OtherDINV[2]# U22

Datasheet 61Package Mechanical Specifications and Pin InformationTable 21. SFF Listing by Ball NameSignal NameBall NumberA[3]# P2A[4]# V4A[5]# W1A[6

Package Mechanical Specifications and Pin Information62 DatasheetD[20]# R41D[21]# W41D[22]# N43D[23]# U41D[24]# AA41D[25]# AB40D[26]# AD40D[27]# AC4

Datasheet 63Package Mechanical Specifications and Pin InformationPSI# BD10PWRGOOD E7REQ[0]# R1REQ[1]# R5REQ[2]# U1REQ[3]# P4REQ[4]# W5RESET# G5RS[0]

Package Mechanical Specifications and Pin Information64 DatasheetVCC AJ33VCC AK16VCC AK18VCC AK20VCC AK22VCC AK24VCC AK26VCC AK28VCC AK30VCC AK32VCC

Datasheet 65Package Mechanical Specifications and Pin InformationVCC BB20VCC BB22VCC BB24VCC BB26VCC BB28VCC BB30VCC BB32VCC BD14VCC BD16VCC BD18VCC

Package Mechanical Specifications and Pin Information66 DatasheetVCC T18VCC T20VCC T22VCC T24VCC T26VCC T28VCC T30VCC T32VCC U33VCC V16VCC V18VCC V2

Datasheet 67Package Mechanical Specifications and Pin InformationVCCP AK14VCCP AK36VCCP AK38VCCP AL7VCCP AL9VCCP AL11VCCP AL13VCCP AL35VCCP AL37VCCP

Package Mechanical Specifications and Pin Information68 DatasheetVCCP R11VCCP R13VCCP R35VCCP R37VCCP T14VCCP U7VCCP U9VCCP U11VCCP U13VCCP U35VCCP

Datasheet 69Package Mechanical Specifications and Pin InformationVSS AD34VSS AD36VSS AD38VSS AD42VSS AE3VSS AE15VSS AE17VSS AE19VSS AE21VSS AE23VSS

Datasheet 7Introduction1 Introduction This document provides electrical, mechanical, and thermal specifications for the Intel® Celeron® Mobile Process

Package Mechanical Specifications and Pin Information70 DatasheetVSS AN21VSS AN23VSS AN25VSS AN27VSS AN29VSS AN31VSS AN39VSS AP6VSS AP8VSS AP34VSS A

Datasheet 71Package Mechanical Specifications and Pin InformationVSS B6VSS B36VSS B42VSS BA1VSS BA3VSS BA9VSS BA11VSS BA13VSS BA15VSS BA17VSS BA19VS

Package Mechanical Specifications and Pin Information72 DatasheetVSS F44VSS G1VSS G3VSS G9VSS G15VSS G17VSS G19VSS G21VSS G23VSS G25VSS G27VSS G29VS

Datasheet 73Package Mechanical Specifications and Pin InformationVSS R29VSS R31VSS R39VSS T6VSS T8VSS T10VSS T12VSS T34VSS T36VSS T38VSS T42VSS U3VS

Package Mechanical Specifications and Pin Information74 Datasheet

Datasheet 75Package Mechanical Specifications and Pin Information4.3 Alphabetical Signals ReferenceTable 22. Signal Description (Sheet 1 of 7)Name Ty

Package Mechanical Specifications and Pin Information76 DatasheetBSEL[2:0] OutputBSEL[2:0] (Bus Select) are used to select the processor input clock f

Datasheet 77Package Mechanical Specifications and Pin InformationDINV[3:0]#Input/OutputDINV[3:0]# (Data Bus Inversion) are source synchronous and indi

Package Mechanical Specifications and Pin Information78 DatasheetFERR#/PBE# OutputFERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiple

Datasheet 79Package Mechanical Specifications and Pin InformationLINT[1:0] InputLINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of

Introduction8 Datasheet1.1 TerminologyTerm Definition#A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the

Package Mechanical Specifications and Pin Information80 DatasheetRESET# InputAsserting the RESET# signal resets the processor to a known state and inv

Datasheet 81Package Mechanical Specifications and Pin Information§ THERMTRIP# OutputThe processor protects itself from catastrophic overheating by use

Package Mechanical Specifications and Pin Information82 Datasheet

Datasheet 83Thermal Specifications and Design Considerations5 Thermal Specifications and Design ConsiderationsMaintaining the proper thermal environme

Thermal Specifications and Design Considerations84 Datasheet3. As measured by the activation of the on-die Intel Thermal Monitor. The Intel Thermal Mo

Datasheet 85Thermal Specifications and Design Considerations5.1.1 Thermal DiodeThe processor incorporates an on-die PNP transistor whose base emitter

Thermal Specifications and Design Considerations86 DatasheetNOTES:1. Intel does not support or recommend operation of the thermal diode under reverse

Datasheet 87Thermal Specifications and Design ConsiderationsNOTES:1. Intel does not support or recommend operation of the thermal diode under reverse

Thermal Specifications and Design Considerations88 DatasheetIf the ntrim value used to calculate the Toffset differs from the ntrim value used to in a

Datasheet 89Thermal Specifications and Design ConsiderationsIntel Thermal Monitor 1 and 2 can co-exist within the processor. If both Intel Thermal Mon

Datasheet 9Introduction1.2 ReferencesMaterial and concepts available in the following documents may be beneficial when reading this document. Document

Thermal Specifications and Design Considerations90 DatasheetUnlike traditional thermal devices, the DTS will output a temperature relative to the maxi

Datasheet 91Thermal Specifications and Design ConsiderationsWhen PROCHOT# is driven by an external agent, if only Intel Thermal Monitor 1 is enabled o

Thermal Specifications and Design Considerations92 Datasheet

Datasheet 11 Coordination of Core-Level Low-Power States at the Package Level... 112 Voltage Identification Definition

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Datasheet 11 Package-Level Low-Power States ... 112 Core Low-Power States

2 Datasheet

Datasheet 11Introduction.......71.1 Terminology

2 Datasheet