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Processor Configuration Registers
206 Datasheet, Volume 2
2.15.18 PHMLIMIT_REG—Protected High-Memory Limit Register
Register to setup the limit address of DMA protected high-memory region. This register
must be setup before enabling protected memory through PMEN_REG, and must not be
updated when protected memory regions are enabled. When LT.CMD.LOCK.PMRC
command is invoked, this register is locked (treated RO). When LT.CMD.UNLOCK.PMRC
command is invoked, this register is unlocked (treated RW). This register is always
treated as RO for implementations not supporting protected high memory region
(PHMR field reported as 0 in the Capability register). The alignment of the protected
high memory region limit depends on the number of reserved bits (N) of this register.
Software may determine the value of N by writing all 1's to this register, and finding
most significant zero bit position below host address width (HAW) in the value read
back from the register. Bits N:0 of the limit register is decoded by hardware as all 1s.
The protected high-memory base and limit registers functions as follows:
• Programming the protected low-memory base and limit registers with the same
value in bits HAW:(N+1) specifies a protected low-memory region of size 2(N+1)
bytes.
• Programming the protected high-memory limit register with a value less than the
protected high-memory base register disables the protected high-memory region.
2.15.19 IQH_REG—Invalidation Queue Head Register
This register indicates the invalidation queue head. This register is treated as reserved
by implementations reporting Queued Invalidation (QI) as not supported in the
Extended Capability register.
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 78–7Fh
Reset Value: 0000000000000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
63:21 RW 00000000
000h
Protected High-Memory Limit (PHML)
This register specifies the last host physical address of the DMA protected
high-memory region in system memory. Hardware may not use bits 63:HAW,
where HAW is the host address width.
20:0 RO 000000h Reserved
B/D/F/Type: 0/0/0/VC0PREMAP
Address Offset: 80–87h
Reset Value: 0000000000000000h
Access: RO
Bit Attr
Reset
Value
Description
63:19 RO 00000000
0000h
Reserved
18:4 RO 0000h Queue Head (QH)
This field specifies the offset (128-bit aligned) to the invalidation queue for
the command that will be fetched next by hardware. Hardware resets this
field to 0 whenever the queued invalidation is disabled (QIES field Clear in
the Global Status register).
3:0 RO 0h Reserved
- Datasheet – Volume 2 1
- Legal Lines and Disclaimers 2
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- 10 Datasheet, Volume 2 10
- Datasheet, Volume 2 11 11
- Revision History 12
- 1 Introduction 13
- Introduction 14
- 2 Processor Configuration 15
- 2.2 System Address Map 17
- 18 Datasheet, Volume 2 18
- 2.2.1 Legacy Address Range 19
- Datasheet, Volume 2 21 21
- 2.2.2.2 TSEG 22
- 2.2.2.5 Pre-allocated Memory 23
- 2.2.2.7 Intel 24
- Management Engine (Intel 24
- ME) UMA 24
- Datasheet, Volume 2 25 25
- 2.2.2.10 High BIOS Area 26
- Datasheet, Volume 2 27 27
- 2.2.3.1 Programming Model 28
- HOST/SYSTEM VIEW 29
- PHYSICAL MEMORY 29
- (DRAM CONTROLLER VIEW) 29
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.2.9 I/O Address Space 35
- 36 Datasheet, Volume 2 36
- Datasheet, Volume 2 37 37
- 2.4 Configuration Mechanisms 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 42 Datasheet, Volume 2 42
- Datasheet, Volume 2 43 43
- 2.6 I/O Mapped Registers 44
- 2.7.6 CC—Class Code Register 49
- TXT Lockable 54
- 1:0 to 11b 56
- 4) from 58
- B0h, bits 15:4) 58
- 2.8 MCHBAR Registers 66
- 00h RW 67
- Register Symbol Register Name 67
- 208–209h 73
- 20A–20Bh 74
- 24D–24Fh 74
- 250-251h 75
- 252–255h 76
- 256–257h 77
- 258–25Ah 77
- 269–26Eh 79
- 298–29Bh 82
- 29C–29Fh 84
- 2B4–2B7h 84
- 600–601h 86
- 602–603h 86
- 604–605h 86
- 64D–64Fh 88
- 650–651h 88
- 652–655h 89
- 656–657h 90
- 658–65Ah 90
- 660–663h 91
- 6B4–6B7h 93
- C20–C27h 94
- 1001–1002h 94
- 1004–1005h 95
- 101E–101Fh 100
- Register 107
- 10EC–10EDh 108
- 2C20–2C22h 109
- 2.9 EPBAR Registers 110
- 2.10 PCI Device 1 Registers 115
- PCI device 117
- Port Command Register 140
- 11:10 RW-O 11b 143
- OS's during run time 155
- 104–107h 156
- 108–10Bh 157
- 10C–10Dh 157
- 110–113h 158
- 23 RO 0b Reserved 158
- 114–117h 158
- 11A–11Bh 159
- 2.12 DMIBAR Registers 161
- Declaration Capability 169
- 2.13.6 CC—Class Code Register 177
- Range Address Register 179
- GMADR register 180
- 2.14 Device 2 I/O Registers 183
- 100–107h 211
- 108–10Fh 212
- 200–20Fh 214
- F00–F03h 215
- F04–F07h 216
- Dedication 217
- F08–F0Bh 218
- FFC–FFFh 219
- 2.16 DMI VC1 REMAP Registers 221
- 2.17.2 GFXPLL1—GFX PLL BIOS 254
- 2.18 GFXVTBAR Registers 255
- Address Register 281
- 2.19 PCI Device 6 Registers 288
- 2.19.45 RSTS—Root Status 327
- 2.21 Intel 332
- Specific Registers 332
- 110–117h 333
- 330–337h 333
- Lower Half Register 334
- Upper Half Register 334
- QuickPath Architecture 335
- System Address Decode 335
- Register Description 335
- QPI Link 0 Registers 340
- QPI Physical 0 Registers 341
- 3.4 PCI Standard Registers 342
- 3.4.4 CCR—Class Code Register 344
- Identification Register 345
- 3.4.7 PCICMD—Command Register 346
- 3.5.1 MAX_RTIDS 349
- 3.6.1 SAD_PAM0123 349
- 3.6.2 SAD_PAM456 351
- 3.6.3 SAD_HEN 352
- 3.6.4 SAD_SMRAM 353
- 3.6.5 SAD_PCIEXBAR 354
- 3.7 Intel 356
- QPI Link Registers 356
- 3.8 Intel 357
- QPI Physical Layer Registers 357
- 360 Datasheet, Volume 2 360
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Liebert Precision Cooling System DS podręczniki
Instrukcje obsługi i podręczniki użytkownika dla Sprzęt komputerowy Liebert Precision Cooling System DS.
Dostarczamy 1 pdf podręczników Liebert Precision Cooling System DS do pobrania za darmo według typów dokumentów: Instrukcja Użytkownika
Liebert Precision Cooling System DS Instrukcja Użytkownika (136 strony)
Marka: Liebert | Kategoria: Hardware | Rozmiar: 5.33 MB |
Spis treści
35"
22
33"
22
Approximate
23
DPN000924
24
TOP VIEW
26
FRONT VIEW
26
DPN001013
28
24"
33
Supply air
37
26"
39
Top of Unit
40
DPN001196
43
Piano Jacks
46
Forklift
46
DETAIL A
51
60-3/16"
57
(1529mm)
57
59-7/16"
60
(1509mm)
60
37"
61
31-1/4"
69
45-13/16"
71
(1163mm)
71
8.0 PIPING
82
INCORRECT
83
CUSTOMER
95
FRONT OF UNIT
101
Front View
101
Section A-A
101
DPN000803
101
Front of Unit
102
DPN000804
102
DPN000900
103
DPN000928
104
DPN000929
105
DPN000933
106
DPN001014
107
DPN001015
108
15-3/16"
109
DPN001119
110
15-7/8"
111
TOP VIEW OF UNIT
112
Top View
113
Front Of Unit
116
DPN001258
116
10.2 Electrical
117
10.3 Piping
117
10.4 Other
117
WARNING
118
12.0 MAINTENANCE
121
Maintenance
124
DPN000996
125
12.7 Compressor
127
Glycol Pump
134
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