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ELECTRICAL SPECIFICATIONS

3.12 System Bus AC Specifications

The system bus timings specified in this section are defined at the processor core pins unless otherwise noted. Timings

are tested at the processor core during manufacturing.

NOTE: Timing specifications T45-T49 are reserved for future use.

All system bus AC specifications for the AGTL+ signal group are relative to the rising edge of the BCLK input. All AGTL+

timings are referenced to 2/3 V

for both ‘0’ and ‘1’ logic levels unless otherwise specified.

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