Intel S5000PSL Manual do Utilizador descarregar pdf (Página 51)

ironmental Specifications Intel® Server Boards S5000PSL and S5000XSL TPS

Revision 1.2

Intel order number: D41763-003

Figure 16. SMBUS Block Diagram

Design and Env

1 2 ... 46 47 48 49 50 51 52 53 54 55 56 ... 119 120

Revision 1.2 1
September 2006 1
Revision History 2
Disclaimers 2
Table of Contents 3
List of Figures 7
List of Tables 8
1. Introduction 11
2. Server Board Overview 13
2.2 Server Board Layout 16
AF000222 25
3. Functional Architecture 26
3.1 Intel 28
3.1.3 Memory Sub-system 31
Slot is not populated 34
Intel® 5000P/5000X Memor 39
Controller Hub 39
3.2.1 PCI Sub-system 41
3.2.2 Serial ATA Support 43
3.3 Video Support 44
3.3.1 Video Modes 46
3.3.3 Dual Video 46
3.4 SAS Controller 47
3.6 Super I/O 48
3.6.1 Serial Ports 49
3.6.4 Wake-up Control 49
3.6.5 System Health Support 49
4. Platform Management 50
5.2 Power Connectors 53
5.3.1 Intel 55
RMM) Connector 55
5.3.2 LCP / AUX IPMB Header 56
5.3.3 IPMB Header 57
5.3.4 HSBP Header 57
5.3.5 SGPIO Header 57
5.3.6 SES I 57
5.4 Front Panel Connector 58
5.5 I/O Connectors 58
5.5.2 NIC Connectors 59
5.5.3 IDE Connector 59
5.5.4 Intel 60
5.5.5 SATA / SAS Connectors 62
5.5.8 USB Connector 64
5.6 Fan Headers 65
6. Jumper Blocks 67
6.3 BIOS Select Jumper 69
AF000224 70
AF000203 71
AF000204 72
Table 36. System Status LED 73
AF000205 75
AF000206 76
8.3.1 Grounding 81
8.3.2 Standby Outputs 81
8.3.3 Remote Sense 81
8.3.4 Voltage Regulation 82
8.3.5 Dynamic Loading 82
8.3.6 Capacitive Loading 83
8.3.7 Ripple / Noise 83
8.3.8 Timing Requirements 83
5VSB_holdup 85
CANADA ICES-003 CLASS A 88
CANADA NMB-003 CLASSE A 88
9.3.2 ICES-003 (Canada) 89
9.3.4 VCCI (Japan) 90
9.3.5 BSMI (Taiwan) 90
9.3.6 RRL (Korea) 90
Compliance 91
Table 46. BMC Sensors 95
Revision 1.2 101
Revision 1.2 111
Appendix D: POST Code Errors 113
POST Error Beep Codes 115
Appendix E: Supported Intel 116
Server Chassis 116
Glossary 117
Reference Documents 120

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