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24 Intel

Xeon

Processor 5600 Series Datasheet Volume 2

Table 2-13. Device 3, Function 4: Integrated Memory Controller Test Registers

DID VID 00h MC_TEST_PH_PIS 80h

PCISTS PCICMD 04h

84h

CCR RID 08h

88h

HDR 0Ch 8Ch

10h 90h

14h 94h

18h 98h

1Ch 9Ch

20h A0h

24h A4h

28h MC_TEST_PAT_GCTR A8h

SID SVID 2Ch

ACh

30h MC_TEST_PAT_BA B0h

34h B4h

38h B8h

3Ch MC_TEST_PAT_IS BCh

40h MC_TEST_PAT_DCD C0h

44h C4h

48h C8h

4Ch CCh

MC_DIMM_CLK_RATIO_STATUS 50h

D0h

MC_DIMM_CLK_RATIO 54h

D4h

58h D8h

5Ch DCh

MC_TEST_ERR_RCV1 60h

E0h

MC_TEST_ERR_RCV0 64h

E4h

68h E8h

MC_TEST_PH_CTR 6Ch

ECh

70h F0h

74h F4h

78h F8h

7Ch FCh

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 63 64

Processor 5600 Series 1
Contents 3
Revision History 6
1 Introduction 7
Introduction 8
2 Register Description 9
2.3 Device Mapping 11
Control Registers 25
Address Registers 26
Rank Registers 27
Thermal Control Registers 28
2.5 PCI Standard Registers 36
2.6.1 DESIRED_CORES 37
2.6.2 MIRROR_PORT_CTL 38
2.7.1 SAD_MCSEG_BASE 39
2.7.2 SAD_MCSEG_MASK 39
2.7.3 SAD_MESEG_BASE 39
2.8 Intel QPI Link Registers 40
2.8.2 QPI_RMT_QPILP1_STAT_L0 41
QPI_RMT_QPILP1_STAT_L1 41
2.8.3 MIP_PH_CTR_L0 41
MIP_PH_CTR_L1 41
2.8.4 MIP_PH_PRT_L0 42
MIP_PH_PRT_L1 42
2.9.2 MC_SMI__CNTRL 43
2.9.3 MC_MAX_DOD 44
2.9.4 MC_RD_CRDT_INIT 45
2.9.5 MC_SCRUBADDR_HI 46
2.10.1 MC_SSRCONTROL 46
2.10.2 MC_SCRUB_CONTROL 46
Registers 47
MC_CHANNEL_1_RANK_TIMING_A 48
MC_CHANNEL_2_RANK_TIMING_A 48
MC_CHANNEL_1_REFRESH_TIMING 50
MC_CHANNEL_2_REFRESH_TIMING 50
2.12 Memory Thermal Control 53
2.12.5 MC_DDR_THERM1_STATUS0 55
MC_DDR_THERM1_STATUS1 55
MC_DDR_THERM1_STATUS2 55
Register Description 56
56 Intel 56
3 Functional Description 57
RAS Modes 61
3.5 Memory Error Signaling 62
3.7 2X Refresh 63
Functional Description 64
64 Intel 64

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