Intel I5 Manual do Utilizador descarregar pdf (Página 46)

46 Specification Update

BU89. VEX.L is Not Ignored with VCVT*2SI Instructions

Problem: The VEX.L bit should be ignored for the VCVTSS2SI, VCVTSD2SI, VCVTTSS2SI, and

VCVTTSD2SI instructions, however due to this erratum the VEX.L bit is not ignored and

will cause a #UD.

Implication: Unexpected #UDs will be seen when the VEX.L bit is set to 1 with VCVTSS2SI,

VCVTSD2SI, VCVTTSS2SI, and VCVTTSD2SI instructions.

Workaround: Software should ensure that the VEX.L bit is set to 0 for all scalar instructions.

Status: For the steppings affected, see the Summary Tables of Changes

BU90. Intel

Turbo Boost Technology May be Incorrectly Reported as

Supported on Intel

Core™ i3-3217U

Problem: The Intel

Core™ i3-3217U processor may incorrectly report support for Intel

Turbo

Boost Technology via CPUID.06H.EAX bit 1.

Implication: The CPUID instruction may report Turbo Boost Technology as supported even though

the processor does not permit operation above the Maximum Non-Turbo Frequency.

Workaround: None identified

Status: For the steppings affected, see the Summary Tables of Changes

BU91. Concurrently Changing the Memory Type and Page Size May Lead to a

System Hang

Problem: Under a complex set of microarchitectural conditions, the system may hang if software

changes the memory type and page size used to translate a linear address while a TLB

(Translation Lookaside Buffer) holds a valid translation for that linear address.

Implication: Due to this erratum, the system may hang. Intel has not observed this erratum with

any commercially available

software.

Workaround: None identified. Please refer to Software Developer’s Manual, volume 3, section

“Recommended Invalidation” for the proper procedure for concurrently changing page

attributes and page size.

Status: For the steppings affected, see the Summary Tables of Changes.

BU92. MCI_ADDR May be Incorrect For Cache Parity Errors

Problem: In cases when a WBINVD instruction evicts a line containing an address or data parity

error (MCACOD of 0x124, and MSCOD of 0x10), the address of this error should be

logged in the MCi_ADDR register.

Due to this erratum, the logged address may be

incorrect, even though MCi_Status.ADDRV (bit 63) is set.

Implication: The address reported in MCi_ADDR may not be correct for cases of a parity error found

during WBINVD execution.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

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