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Register and Memory Mapping
Intel
®
Atom™ Processor E6xx Series Datasheet
53
5.0 Register and Memory Mapping
This chapter describes the I/O and memory map settings for the Intel
®
Atom™
Processor E6xx Series in the MCP.
5.1 Address Map
The Intel
®
Atom™ Processor E6xx Series contains registers that are located in the
processor’s memory and I/O space. It also contains sets of PCI configuration registers
that are located in a separate configuration space.
5.2 Introduction
The Intel
®
Atom™ Processor E6xx Series contains two sets of software accessible
registers accessed via the host processor I/O address space: Control registers and
internal configuration registers.
Table 35. Register Access Types and Definitions
Access Type Meaning Description
RO Read Only
In some cases, if a register is read only, writes to this
register location have no effect. However, in other cases,
two separate registers are located at the same location
where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map
tables for details.
WO Write Only
In some cases, if a register is write only, reads to this
register location have no effect. However, in other cases,
two separate registers are located at the same location
where a read accesses one of the registers and a write
accesses the other register. See the I/O and memory map
tables for details.
R/W Read/Write A register with this attribute can be read and written.
R/WC Read/Write Clear
A register bit with this attribute can be read and written.
However, a write of 1 clears (sets to 0) the corresponding
bit and a write of 0 has no effect.
R/WO Read/Write-Once
A register bit with this attribute can be written only once
after power up. After the first write, the bit becomes read
only.
R/WLO
Read/Write, Lock-
Once
A register bit with this attribute can be written to the non-
locked value multiple times, but to the locked value only
once. After the locked value has been written, the bit
becomes read only.
Default Default
When the processor is reset, it sets its registers to
predetermined default states. The default state represents
the minimum functionality feature set required to
successfully bring up the system. Hence, it does not
represent the optimal system configuration. It is the
responsibility of the system initialization software to
determine configuration, operating parameters, and
optional system features that are applicable, and to
program the processor registers accordingly.
- Atom™ Processor E6xx Series 1
- Legal Lines and Disclaimers 2
- Contents 10
- Revision History 21
- Segment dependent PCIe* 23
- 1.1 Terminology 24
- 1.2 Reference Documents 25
- Intel® Atom™ Processor 26
- E6xx Series 26
- 1.3.1 Low-Power Intel 27
- Architecture Core 27
- 1.3.3 Graphics 27
- 1.3.6.1 LVDS Interface 28
- Introduction 29
- 2.0 Signal Description 31
- 2.1 System Memory Signals 32
- 2.2.1 LVDS Signals 33
- 2.3 PCI Express* Signals 35
- 2.4 Intel 35
- Interface Signals 35
- 2.5 LPC Interface Signals 36
- 2.6 SMBus Interface Signals 36
- 2.7 SPI Interface Signals 36
- 2.10 JTAG and Debug Interface 38
- 2.12 General Purpose I/O 42
- 2.13 Functional Straps 42
- 2.14 Power and Ground Signals 43
- 3.0 Pin States 45
- 3.3.1 LVDS Signals 46
- 3.4 PCI Express* Signals 47
- 3.5 Intel 47
- 3.6 LPC Interface Signals 48
- 3.7 SMBus Interface Signals 48
- 3.8 SPI Interface Signals 48
- 3.11 JTAG and Debug Interface 49
- 3.13 General Purpose I/O 50
- 4.0 System Clock Domains 51
- System Clock Domains 52
- 5.1 Address Map 53
- 5.2 Introduction 53
- 5.3 System Memory Map 54
- Figure 3. System Address Map 55
- 5.3.1 I/O Map 56
- 5.4.1.1 Hard Coded IO Access 58
- 5.4.1.2 IO BAR 59
- 5.4.1.4 Memory BAR 59
- 5.4.2.1 PCI Config Space 59
- : 0000h - 0003h 60
- P – Device 3 Interrupt Pin 64
- R – Device 31 Interrupt Route 64
- 5.5.4 General Configuration 67
- Register and Memory Mapping 68
- 6.0 Memory Controller 69
- 6.5 Refresh Mode 70
- 6.7 Supported DRAM Devices 72
- Atom™ Processor E6xx Series 75
- Graphics, Video, and Display 76
- 7.2.3.2 Lighting Stages 77
- 7.2.4 Pixel Processing 78
- 7.2.5 Unified Shader 78
- 7.3.1.1 Encoding Pipeline 79
- 7.3.1.2 Encode Codec Support 80
- 7.4 Video Decode 81
- 7.4.1.1 Motion Compensation 82
- 7.4.1.2 Deblocking 82
- 7.4.1.4 Pixel Format 83
- Controller 84
- 7.5.1.1 Planes 85
- 7.5.1.2 Display Pipes 86
- 7.5.2.1 LVDS Port 87
- 7.5.2.4 SDVO DVI/HDMI 89
- 7.7 Configuration Registers 90
- 8.1.2.1 Sleep State Support 111
- 8.1.2.4 SMI/SCI Generation 112
- VID — Vendor Identification 113
- 8.2.1.3 CMD — PCI Command 114
- 8.2.1.4 PSTS — Primary Status 114
- DID — Device Identification 114
- CMD — PCI Command 114
- 8.2.1.6 CC — Class Code 115
- PSTS — Primary Status 115
- 8.2.1.7 CLS — Cache Line Size 116
- 8.2.1.8 HTYPE — Header Type 116
- PBN — Primary Bus Number 116
- — I/O Limit Address 118
- 8.2.1.21 IPIN — Interrupt Pin 121
- 01 0b RW SE 122
- 8.2.2.4 DCTL — Device Control 124
- 8.2.2.5 DSTS — Device Status 125
- 8.2.2.7 LCTL — Link Control 126
- 8.2.2.8 LSTS — Link Status 126
- 8.2.2.10 SLCTL — Slot Control 127
- 8.2.2.11 SLSTS — Slot Status 128
- 8.2.2.12 RCTL — Root Control 129
- 8.2.2.14 RSTS — Root Status 129
- RCAP — Root Capabilities 129
- 8.2.5 Port Configuration 132
- FD — Functional Disable 135
- PCI Express* 136
- 9.0 Intel 137
- High Definition Audio 137
- 9.2.1 Dock Sequence 138
- 9.2.2 Undock Sequence 139
- 9.3.1 Registers 140
- Table 177. Intel 141
- Control Register 147
- Register 148
- Capability Header Register 156
- 9.3.2.1 Intel 157
- HD Audio 157
- Registers 157
- Table 225. Intel 158
- GCTL – Global Control 162
- (Sheet 2 of 2) 182
- 10.0 LPC Interface (D31:F0) 187
- 10.2.1 ID—Identifiers 188
- 10.2.5 CC—Class Code Register 190
- 10.4 Interrupt Control 195
- 10.4.3 WDTBA-WDT Base Address 196
- 10.5.2 BDE—BIOS Decode Enable 197
- LPC Interface (D31:F0) 200
- 11.0 ACPI Devices 201
- 11.1.5.1 Read Back Command 202
- 11.1.6 Timer Programming 204
- 11.1.7.1 Simple Read 205
- 11.1.7.3 Read Back Command 206
- Capabilities 208
- 11.2.2 Theory Of Operation 210
- 11.2.2.3 Interrupts 211
- 11.3.1 Overview 212
- 11.3.2 I/O Registers 213
- 11.3.3.1 Generating 218
- 11.3.3.2 Acknowledging 218
- 11.3.4.1 ICW1 219
- 11.3.4.2 ICW2 220
- 11.3.4.3 ICW3 220
- 11.3.4.4 ICW4 220
- 11.3.6.1 Fully Nested Mode 220
- 11.3.6.5 Poll Mode 221
- 11.3.7.1 Normal EOI 222
- 11.3.7.2 Automatic EOI 222
- 11.3.8.2 Special Mask Mode 222
- 11.4.1 Memory Registers 223
- 11.4.2 Index Registers 224
- 11.4.4.1 Theory of Operation 226
- 11.4.4.2 EOI 226
- 11.5 Serial Interrupt 227
- 11.5.2 Start Frame 228
- 11.5.3 Data Frames 228
- 11.5.4 Stop Frame 228
- 11.6 Real Time Clock 230
- : Register A 231
- 11.6.4 Update Cycles 233
- 11.6.5 Interrupts 233
- 11.7 General Purpose I/O 234
- 11.7.3.1 Power Wells 240
- 11.7.3.2 SMI# and SCI Routing 240
- 11.7.3.3 Triggering 240
- 11.8 SMBus Controller 241
- 11.8.3 Overview 244
- 11.8.5.1 Clock Stretching 245
- 11.8.5.2 Bus Time Out 246
- 11.9.4 SPI Protocol 247
- 11.9.5 Host Side Interface 249
- SPIA – SPI Address 252
- ACPI Devices 256
- 11.9.5.14 Flash Protection 258
- Control Register. This is 259
- 11.9.6 SPI Clocking 260
- 11.9.7.1 Run Time Updates 261
- 11.9.7.2 BIOS Sector Updates 261
- 11.9.7.3 SPI Initialization 262
- 11.10 Watchdog Timer 263
- 11.10.4 Theory Of Operation 270
- 11.10.4.3 Reload Sequence 271
- 11.10.4.4 Low Power State 271
- 12.0 Absolute Maximum Ratings 273
- 12.1 Absolute Maximum Rating 274
- 13.0 DC Characteristics 275
- 14.1 Package Diagrams 282
- Figure 11. Intel 283
- Figure 12. Intel 284
- Figure 13. Intel 285
- Figure 14. Intel 286
- Figure 15. Intel 287
- Figure 16. Intel 288
- Figure 17. Intel 289
- Table 407. Pin List 290
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