Intel core 2 Duo T5850 Especificações descarregar pdf (Página 113)

Intel

64 and IA-32 Architectures Software Developer’s Manual Documentation Changes 113

Documentation Changes

ORPD—Bitwise Logical OR of Double-Precision Floating-Point Values

Instruction Operand Encoding

...

ORPS—Bitwise Logical OR of Single-Precision Floating-Point Values

Instruction Operand Encoding

...

OUT—Output to Port

Opcode Instruction Op/

64-Bit

Mode

Compat/

Leg Mode

Description

66 0F 56 /r ORPD xmm1,

xmm2/m128

A Valid Valid Bitwise OR of xmm2/m128

and xmm1.

Op/En Operand 1 Operand 2 Operand 3 Operand 4

A ModRM:reg (r, w) ModRM:r/m (r) NA NA

Opcode Instruction Op/

64-Bit

Mode

Compat/

Leg Mode

Description

0F 56 /r ORPS xmm1,

xmm2/m128

A Valid Valid Bitwise OR of xmm2/m128

and xmm1.

Op/En Operand 1 Operand 2 Operand 3 Operand 4

A ModRM:reg (r, w) ModRM:r/m (r) NA NA

Opcode* Instruction Op/

64-Bit

Mode

Compat/

Leg Mode

Description

E6 ib OUT imm8, AL A Valid Valid Output byte in AL to I/O port

address imm8.

E7 ib OUT imm8, AX A Valid Valid Output word in AX to I/O

port address imm8.

E7 ib OUT imm8, EAX A Valid Valid Output doubleword in EAX

to I/O port address imm8.

EE OUT DX, AL B Valid Valid Output byte in AL to I/O port

address in DX.

EF OUT DX, AX B Valid Valid Output word in AX to I/O

port address in DX.

EF OUT DX, EAX B Valid Valid Output doubleword in EAX

to I/O port address in DX.

NOTES:

* See IA-32 Architecture Compatibility section below.

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