Intel SL2YM Ficha Técnica descarregar pdf (Página 34)

Pentium

II Processor at 350 MHz, 400 MHz, and 450 MHz

34 Datasheet

Figure 6. BCLK, PICCLK, and TCK Generic Clock Waveform

Figure 7. System Bus Valid Delay Timings

Figure 8. System Bus Setup and Hold Timings

000761a

1.7V (2.0V*)

1.25V

0.7V (0.5V*)

CLK

= T5, pT25, T34 (Rise Time)

= T6, T26, T35 (Fall Time)

= T3, T23, T32 (High Time)

= T4, T24, T33 (Low Time)

= T1, T22, T31 (BLCK, TCK, PCICLK Period)

Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK and TCK are referenced to

0.7 V and 1.7 V

CLK

Signal

000762b

V Valid Valid

T7, T11, T29 (Valid Delay)

T14, T15 (Pulse Wdith)=

1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups=

CLK

Signal

000763b

VValid

T8, T12, T27 (Setup Time)=

T9, T13, T28 (Hold Time)=

1.0V for GTL+ signal group; 1.25V for CMOS, APIC and JTAG signal groups=

1 2 ... 29 30 31 32 33 34 35 36 37 38 39 ... 83 84

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