Intel RH80532GC033512 Ficha Técnica descarregar pdf (Página 58)

System Bus Signal Quality Specifications

58 Mobile Intel



Pentium



4 Processor-M Datasheet

NOTES:

1. These specifications are measured at the processor core silicon.

2. BCLK period is 10 ns.

NOTES:

1. These specifications are measured at the processor core silicon.

2. BCLK period is 10 ns.

Table 31. Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot

Tolerance

Absolute

Maximum

Overshoot

(V)

Absolute

Maximum

Undershoot

(V)

Pulse

Duration (ns)

AF = 1

Pulse

Duration (ns)

AF = 0.1

Pulse

Duration (ns)

AF = 0.01

Notes

1,2

1.700 -0.400 0.21 2.10 10.00

1.650 -0.350 0.48 4.80 10.00

1.600 -0.300 1.05 10.00 10.00

1.550 -0.250 2.38 10.00 10.00

1.500 -0.200 10.00 10.00 10.00

1.450 -0.150 10.00 10.00 10.00

1.400 -0.100 10.00 10.00 10.00

1.350 -0.050 10.00 10.00 10.00

Table 32. Common Clock (100 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance

Absolute

Maximum

Overshoot

(V)

Absolute

Maximum

Undershoot

(V)

Pulse

Duration (ns)

AF = 1

Pulse

Duration (ns)

AF = 0.1

Pulse

Duration (ns)

AF = 0.01

Notes

1,2

1.700 -0.400 0.42 4.20 20.00

1.650 -0.350 0.96 9.60 20.00

1.600 -0.300 2.10 20.00 20.00

1.550 -0.250 4.76 20.00 20.00

1.500 -0.200 20.00 20.00 20.00

1.450 -0.150 20.00 20.00 20.00

1.400 -0.100 20.00 20.00 20.00

1.350 -0.050 20.00 20.00 20.00

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 96 97

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