Intel LF80537NF0411M Ficha Técnica

Mobile Intel® Celeron® Processor on .13 Micron Process in Micro-FCPGA Package Specification Update October 2005 Notice: The mobile In

R 10 Specification Update Steppings NO. B0 C1 D1 Plans ERRATA V15 X Fixed Incorrect data may be returned when page tables are in Write Combinin

R Specification Update 11 Steppings NO. B0 C1 D1 Plans ERRATA HardFailure Response May Hang the Processor V40 X X X NoFix Memory Type of the Load

R 12 Specification Update Identification Information The mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA package can be ide

R Specification Update 13 Table 1. Mobile Intel® Celeron® Processor Identification Information S-Spec Product Stepping L2 Cache Size (bytes) CPU

R 14 Specification Update Component Marking Information Figure 1. Mobile Intel® Celeron® Processor on .13 Micron Process (Micro-FCPGA) Markings

R Specification Update 15 Errata V1. I/O Restart in SMM may Fail after Simultaneous Machine Check Exception (MCE) Problem: If an I/O instructio

R 16 Specification Update V3. Transaction Is Not Retried after BINIT# Problem: If the first transaction of a locked sequence receives a HITM# an

R Specification Update 17 V6. The Processor Signals Page-Fault Exception (#PF) Instead of Alignment Check Exception (#AC) on an Unlocked CMPXCHG8

R 18 Specification Update V9. The IA32_MC1_STATUS Register May Contain Incorrect Information for Correctable Errors Problem: When a speculative

R Specification Update 19 V11. Machine Check Architecture Error Reporting and Recovery May Not Work As Expected Problem: When the processor dete

R 2 Specification Update INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS

R 20 Specification Update may latch invalid information. - If RESET# is asserted, then de-asserted, and reasserted, before the processor has clea

R Specification Update 21 V13. EMON Event Counting of x87 Loads May Not Work As Expected Problem: If a performance counter is set to count x87 l

R 22 Specification Update V17. Multiple Accesses to the Same S-State L2 Cache Line and ECC Error Combination May Result in Loss of Cache Coherenc

R Specification Update 23 V20. Associated Counting Logic Must Be Configured When Using Event Selection Control (ESCR) MSR Problem: ESCR MSRs all

R 24 Specification Update V23. BPM[5:3]# and GHI# VIL Does Not Meet Specification Problem: The VIL for BPM[5:3]# and GHI# is specified as 0.9 *

R Specification Update 25 V26. L2 Cache May Contain Stale Data in the Exclusive State Problem: If a cacheline (A) is in Modified (M) state in th

R 26 Specification Update V28. Erroneous BIST Result Found in EAX Register after Reset Problem: The processor may show an erroneous BIST (built-

R Specification Update 27 V32. CPUID Instruction Returns Incorrect Number of ITLB Entries Problem: When CPUID is executed with EAX = 2 it should

R 28 Specification Update V35. Parity Error in the L1 Cache may Cause the Processor to Hang Problem: If a locked operation accesses a line in th

R Specification Update 29 V38. Changes to CR3 Register do not Fence Pending Instruction Page Walks Problem: When software writes to the CR3 re

R Specification Update 3 Contents Revision History...

R 30 Specification Update V41. A 16-bit Address Wrap Resulting from a Near Branch (Jump or Call) May Cause an Incorrect Address to Be Reported t

R Specification Update 31 V44. Memory Aliasing of Pages as Uncacheable Memory Type and Write Back (WB) May Hang the System Problem: When a page

R 32 Specification Update V47. BTS(Branch Trace Store) and PEBS(Precise Event Based Sampling) May Update Memory outside the BTS/PEBS Buffer Prob

R Specification Update 33 V49. Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction with Fast Strings Enabled Problem: Un

R 34 Specification Update Specification Clarifications The Specification Clarifications listed in this section apply to the following documents:

R Specification Update 35 RESET, the counter will increment even when the processor is halted by the HLT instruction or the external STPCLK# pin.

R 36 Specification Update Technology is enabled, both logical processors must be halted for performance-monitoring counters to be powered down. •

R Specification Update 37 Specification Changes The Specification Changes listed in this section apply to the following documents: • Mobile Inte

R 38 Specification Update V2. BR0# Maximum Hold Time Specification Change The BR0# maximum hold time has changed to 2 BCLKs. This change will b

R Specification Update 39 The following figure will be modified to reflect this change: Figure 12. System Bus Reset and Configuration Timings B

R 4 Specification Update Revision History Revision Number Description Date -001 Initial Release June 2002 -002 Updated Identification Informat

R 40 Specification Update Documentation Changes The Documentation Changes listed in this section apply to the following documents: • Mobile Inte

R Specification Update 5 -027 Updated Related Documents table July 2005 -028 Added errata V50 and updated Processor Identification Table. Oct

R 6 Specification Update Preface This document is an update to the specifications contained in the document listed in the following Affected/Rela

R Specification Update 7 Nomenclature S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique c

R 8 Specification Update Summary of Changes The following table indicates the Errata, Documentation Changes, Specification Clarifications, or Spe

R Specification Update 9 L = Intel ® Celeron ® D processor M = Mobile Intel ® Celeron ® processor N = Intel ® Pentium ® 4 processor O = Intel ®