Intel JM80547PG0961MM Ficha Técnica descarregar pdf (Página 27)

Intel

Pentium

4 Processor in the 423-pin Package

Figure 5. Differential Clock Waveform

Figure 6. System Bus Common Clock Valid Delay Timings

Crossing

Voltage

Threshold

Region

Overshoot

Undershoot

Ringback

Margin

Rising Edge

Ringback

Falling Edge

Ringback,

BCLK0

BCLK1

Crossing

Voltage

Tph

Tpl

Tp = T1 (BCLK[1:0] period)

T2 = BCLK[1:0] Period stability (not shown)

Tph =T3 (BCLK[1:0] pulse high time)

Tpl = T4 (BCLK[1:0] pulse low time)

T5 = BCLK[1:0] rise time through the threshold region (not shown)

T6 = BCLK[1:0] fall time through the threshold region (not shown)

BCLK0

BCLK1

Common Clock

Signal (@ driver)

Common Clock

Signal (@ receiver)

T1 T2

valid valid

valid

= T10: T

(Data Valid Output Delay)

= T11: T

(Common Clock Setup)

= T12: T

(Common Clock Hold Time)

1 2 ... 22 23 24 25 26 27 28 29 30 31 32 ... 89 90

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Intel JM80547PG0961MM Ficha Técnica Página 27

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