Intel I5 Manual do Utilizador

Reference Number: 326766Desktop 3rd Generation Intel® Core™ Processor Family Specification UpdateSeptember 2013Revision 015

10 Specification UpdateBV33XXXNo FixClock Modulation Duty Cycle Cannot be Programmed to 6.25%BV34XXXNo FixProcessor May Fail to Acknowledge a TLP Requ

Specification Update 11BV60XXXNo FixThe Processor May Not Comply With PCIe* Equalization Preset Reflection Requirements for 8 GT/s Mode of OperationB

12 Specification UpdateBV90XXXNo FixDuring Package Power States Repeated PCIe* and/or DMI L1 Transitions May Cause a SystemBV91XXXNo FixInstruction Fe

Specification Update 13§ §Documentation ChangesNumber DOCUMENTATION CHANGESBU1On-Demand Clock Modulation Feature Clarification

14 Specification UpdateIdentification InformationComponent Identification using Programming InterfaceThe processor stepping can be identified by the f

Specification Update 15Component Marking InformationThe processor stepping can be identified by the following component markings.Figure 1. Processor

16 Specification UpdateSR0P3 i5-3550S E-1 000306A9h 3 / 1600 / 6504 core: 3.33 core: 3.42 core: 3.61 core: 3.76 3,4,5,6SR0PM i5-3570K E-1 000306A9h 3.

Specification Update 17SR0PC E3-1290V2 E-1 000306A9h 3.7 / 1600 / 04 core: 3.83 core: 3.92 core: 41 core: 4.18 2,3,4,5,6SR0P7 E3-1280V2 E-1 000306A9h

18 Specification UpdateSR0RG i3-3220 L-1 000306A9h 3.3 / 1600 / 6504 core: N/A3 core: N/A2 core: N/A1 core: 3.332, 4SR0RE i3-3220T L-1 000306A9h 2.8

Specification Update 19SR0PL i7-3770K E-1 000306A9h 3.5/ 1600/ 6504 core: 3.73 core: 3.82 core: 3.91 core: 3.982,4,6SR0PN i7-3770S E-1 000306A9h 3.1/

2 Specification UpdateINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER

20 Specification UpdateNotes:1. This column indicates maximum Intel® Turbo Boost Technology 2.0 frequency (GHz) for 4,3, 2 or 1 cores active respectiv

Specification Update 21ErrataBV1. The Processor May Report a #TS Instead of a #GP FaultProblem: A jump to a busy TSS (Task-State Segment) may cause a

22 Specification UpdateBV4. Performance Monitor SSE Retired Instructions May Return Incorrect ValuesProblem: Performance Monitoring counter SIMD_INST_

Specification Update 23BV8. LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit ModeProblem: An exception/interrupt

24 Specification UpdateBV11. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation ChangeProblem: This erratum is regardin

Specification Update 25BV13. MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB ErrorProblem: A single Data Translation Lo

26 Specification UpdateBV17. PEBS Record not Updated when in Probe ModeProblem: When a performance monitoring counter is configured for PEBS (Precise

Specification Update 27BV21. #GP on Segment Selector Descriptor that Straddles Canonical Boundary May Not Provide Correct Exception Error CodeProblem

28 Specification UpdateBV24. Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering ViolationsProblem: Under complex micr

Specification Update 29BV27. Fault Not Reported When Setting Reserved Bits of Intel® VT-d Queued Invalidation DescriptorsProblem: Reserved bits in th

ContentsSpecification Update 3ContentsRevision History...

30 Specification UpdateBV30. Spurious Interrupts May be Generated From the Intel® VT-d Remap EngineProblem: If software clears the F (Fault) bit 127 o

Specification Update 31BV34. Processor May Fail to Acknowledge a TLP RequestProblem: When a PCIe root port’s receiver is in Receiver L0s power state

32 Specification UpdateBV38. PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have OccurredProblem: Under very specific timing cond

Specification Update 33BV41. PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the SpecificationProblem: Under certain conditions, inc

34 Specification UpdateBV44. IA32_FEATURE_CONTROL MSR May be Uninitialized on a Cold ResetProblem: IA32_FEATURE_CONTROL MSR (3Ah) may have random valu

Specification Update 35BV48. 64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI Before Any Data is TransferredProblem: If a REP M

36 Specification UpdateBV52. Instructions Retired Event May Over Count Execution of IRET InstructionsProblem: Under certain conditions, the performanc

Specification Update 37BV56. PCI Express* Gen3 Receiver Return Loss May Exceed SpecificationsProblem: The PCIe Base Specification includes a graph th

38 Specification UpdateBV59. PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During UpconfigurationProblem: The processor s

Specification Update 39BV63. PCIe* Root-port Initiated Compliance State Transmitter Equalization Settings May be IncorrectProblem: If the processor i

Contents4 Specification Update

40 Specification UpdateBV67. MSR_PKG_Cx_RESIDENCY MSRs May Not be AccurateProblem: If the processor is in a package C-state for an extended period of

Specification Update 41BV71. PCIe* Root Port May Not Initiate Link Speed ChangeProblem: The PCIe Base specification requires the upstream component t

42 Specification UpdateBV74. VM Exits Due to “NMI-Window Exiting” May Not Occur Following a VM Entry to the Shutdown StateProblem: If VM entry is made

Specification Update 43BV77. PCIe* Controller May Not Enter LoopbackProblem: The PCIe controller is expected to enter loopback if any lane in the lin

44 Specification UpdateBV81. PCIe* Link May Fail Link Width UpconfigurationProblem: The processor supports PCIe Hardware Autonomous Width management,

Specification Update 45BV85. Performance-Counter Overflow Indication May Cause Undesired BehaviorProblem: Under certain conditions (listed below) whe

46 Specification UpdateBV88. Concurrently Changing the Memory Type and Page Size May Lead to a System HangProblem: Under a complex set of microarchite

Specification Update 47BV92. The Processor May Not Properly Execute Code Modified Using A Floating-Point StoreProblem: Under complex internal conditi

48 Specification UpdateBV96. IA32_MC5_CTL2 is Not Cleared by a Warm ResetProblem: IA32_MC5_CTL2 MSR (285H) is documented to be cleared on any reset. D

Specification Update 49BV98. Performance Monitor Counters May Produce Incorrect ResultsProblem: When operating with SMT enabled, a memory at-retireme

Specification Update 5Revision HistoryRevision Description Date001 • Initial Release. April 2012002• Added Errata BV68–BV83• Updated Processor Identi

50 Specification UpdateBV100. Spurious VT-d Interrupts May Occur When the PFO Bit is SetProblem: When the PFO (Primary Fault Overflow) field (bit [0]

Specification Update 51BV104. EPT Violations May Report Bits 11:0 of Guest Linear Address IncorrectlyProblem: If a memory access to a linear address

52 Specification UpdateBV108. Virtual-APIC Page Accesses With 32-Bit PAE Paging May Cause a System CrashProblem: If a logical processor has EPT (Exten

Specification Update 53Specification ChangesThe Specification Changes listed in this section apply to the following documents:•Intel® 64 and IA-32 Ar

54 Specification UpdateSpecification ClarificationsThe Specification Clarifications listed in this section may apply to the following documents:•Intel

Specification Update 55Documentation ChangesThe Documentation Changes listed in this section apply to the following documents:•Intel® 64 and IA-32 Ar

56 Specification Update§ §DisplayFamily_DisplayModel DisplayFamily_DisplayModel DisplayFamily_DisplayModel DisplayFamily_DisplayModel 0F_xx 06_1C 06_1

6 Specification UpdatePrefaceThis document is an update to the specifications contained in the Affected Documents table below. This document is a comp

Specification Update 7NomenclatureErrata are design defects or errors. These may cause the processor behavior to deviate from published specification

8 Specification UpdateSummary Tables of ChangesThe following tables indicate the errata, specification changes, specification clarifications, or docum

Specification Update 9BV7XXXNo FixGeneral Protection Fault (#GP) for Instructions Greater than 15 Bytes May be PreemptedBV8XXXNo FixLBR, BTS, BTM May