Intel CP80617004803AA Ficha Técnica descarregar pdf (Página 39)

Datasheet 39

Power Management

4.1.3 Integrated Memory Controller States

4.1.4 PCIe Link States

4.1.5 DMI States

4.1.6 Integrated Graphics Controller States

Table 4-7. Integrated Memory Controller States

State Description

Power up CKE asserted. Active mode.

Pre-charge Power down CKE deasserted (not self-refresh) with all banks closed.

Active Power down CKE deasserted (not self-refresh) with minimum one bank active.

Self-Refresh CKE deasserted using device self-refresh.

Table 4-8. PCIe Link States

State Description

L0 Full on  Active transfer state.

L0s First Active Power Management low power state  Low exit latency.

L1 Lowest Active Power Management - Longer exit latency.

L3 Lowest power state (power-off)  Longest exit latency.

Table 4-9. DMI States

State Description

L0 Full on  Active transfer state.

L0s First Active Power Management low power state  Low exit latency.

L1 Lowest Active Power Management - Longer exit latency.

L3 Lowest power state (power-off)  Longest exit latency.

Table 4-10.Integrated Graphics Controller States

State Description

D0 Full on, display active.

D3 Cold Power-off.

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 180 181

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Intel CP80617004803AA Ficha Técnica Página 39