Intel AV8062701048800 Ficha Técnica descarregar pdf (Página 37)

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Intel

Xeon

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Core™ Processors For Communications Infrastructure

May 2012 Datasheet - Volume 1 of 2

Document Number: 327405

-001 37

• Allow communication of processor thermal and other information to the PECI

master.

• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.

3.5 Interface Clocking

3.5.1 Internal Clocking Requirements

§ §

Table 3-7. Reference Clock

Reference Input Clock Input Frequency Associated PLL

BCLK/BCLK# 100 MHz Processor/Memory/PCIe/DMI

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 163 164

May 2012 1
Legal Lines and Disclaimers 2
Revision History 3
Contents 4
1.0 Introduction 11
1.3 Terminology 13
2.0 Product Overview 15
Processor 16
2.1 Product Features 17
2.2 Processor Details 17
2.3 Supported Technologies 17
2.4 Interface Features 17
2.4.2 PCI Express* 18
2.5 Power Management Support 21
2.7 Package 21
2.8 Testability 21
3.0 Interfaces 23
3.1.1.1 UDIMM Configurations 24
3.1.3.1 Single-Channel Mode 27
Flex Memory Technology Mode 27
Fast Memory Access 28
3.1.5.2 Command Overlap 29
3.2.1.1 Transaction Layer 31
3.2.1.2 Data Link Layer 31
3.2.1.3 Physical Layer 31
3.2.5 Configuring PCIe* Lanes 35
3.3 Direct Media Interface 36
3.5 Interface Clocking 37
4.0 Technologies 39
4.1.3 Intel 40
VT-d Objectives 40
4.1.4 Intel 40
VT-d Features 40
4.2 Intel 41
Hyper-Threading Technology 41
4.3 Intel 41
4.4.1 PCLMULQDQ Instruction 42
5.0 Processor SKUs 45
6.0 Power Management 47
6.1 ACPI States Supported 48
6.1.4 PCIe* Link States 49
6.1.5 DMI States 49
Processor Package State 50
Core 1 State 50
Thread 1Thread 0 50
Core 0 State 50
C1 C1E C7C6C3 51
6.2.4.1 Core C0 State 52
6.2.4.2 Core C1/C1E State 52
6.2.4.3 Core C3 State 53
6.2.4.4 Core C6 State 53
6.2.4.5 Core C7 State 53
6.2.4.6 C-State Auto-Demotion 53
6.2.5.1 Package C0 55
6.2.5.2 Package C1/C1E 55
6.2.5.3 Package C3 State 56
6.2.5.4 Package C6 State 56
6.2.5.5 Package C7 State 56
6.3 IMC Power Management 57
6.5 DMI Power Management 59
6.6 Thermal Power Management 59
6.4 PCIe* Power Management 59
7.0 Thermal Management 61
Table 7-1. TDP Specifications 62
7.3.1.3 PROCHOT# Signal 66
7.3.2.1 On-Demand Mode 68
8.0 Signal Description 71
8.6 PLL Signals 76
8.7 TAP Signals 76
8.9 Power Sequencing 78
8.11 Sense Pins 79
8.12 Future Compatibility 79
9.0 Electrical Specifications 81
9.3.1 PLL Power Supply 82
9.5 System Agent (SA) Vcc VID 89
9.7 Signal Groups 90
9.10 DC Specifications 93
± 200mV and the edge must be 98
9.11 AC Specifications 101
9.11.1 DDR3 AC Specifications 103
= 1.5 V ±0.075 V 104
-001 105 105
-001 107 107
Cl ock-Cl ock# 110
Programmable 111
Vref + 100mV 112
Vref – 100mV 112
-001 113 113
9.14.1 V 115
Overshoot Specification 115
Voltage (V) 116
-001 117 117
-001 121 121
-001 123 123
-001 125 125
-001 127 127
-001 129 129
-001 131 131
-001 133 133
-001 135 135
-001 137 137
-001 139 139
-001 141 141
-001 143 143
-001 145 145
-001 147 147
-001 149 149
11.1 ERRSTS - Error Status 152
11.2 ERRCMD - Error Command 153
11.3 SMICMD - SMI Command 154
11.4 SCICMD - SCI Command 155
40CC-40CFh 156
44C8-44CBh 157
44CC-44CFh 158
5004-5007h 158
5008-500Bh 160
-001 163 163

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