Intel D15343-003 Manual do Utilizador

Intel® 82854 Graphics Memory Controller Hub (GMCH) DatasheetRevision 2.0June 2005Order Number: D15343-003

10 D15343-003Intel® 82854 Graphics Memory Controller Hub (GMCH)

Intel® 82854 Graphics Memory Controller Hub (GMCH)100 D15343-0034.11 Intel® 82854 GMCH Integrated Graphics Device Registers (Device #2, Function #0)

Register DescriptionD15343-003 1014.11.1 VID – Vendor Identification Register (Device #2)The VID Register contains the vendor identification number.

Intel® 82854 Graphics Memory Controller Hub (GMCH)102 D15343-0034.11.3 PCICMD – PCI Command Register (Device #2)This 16-bit register provides basic

Register DescriptionD15343-003 1034.11.4 PCISTS – PCI Status Register (Device #2)PCISTS is a 16-bit status register that reports the occurrence of a

Intel® 82854 Graphics Memory Controller Hub (GMCH)104 D15343-0034.11.6 CC – Class Code Register (Device #2)This register contains the device program

Register DescriptionD15343-003 1054.11.9 HDR – Header Type Register (Device #2)This register contains the Header Type of the IGD.4.11.10 GMADR – Gra

Intel® 82854 Graphics Memory Controller Hub (GMCH)106 D15343-0034.11.11 MMADR – Memory Mapped Range Address Register (Device #2)This register reques

Register DescriptionD15343-003 1074.11.13 SVID – Subsystem Vendor Identification Register (Device #2)4.11.14 SID – Subsystem Identification Register

Intel® 82854 Graphics Memory Controller Hub (GMCH)108 D15343-0034.11.16 INTRLINE – Interrupt Line Register (Device #2)4.11.17 INTRPIN – Interrupt Pi

Register DescriptionD15343-003 1094.11.19 MAXLAT – Maximum Latency Register (Device #2)4.11.20 PMCAP – Power Management Capabilities Register (Devic

IntroductionD15343-003 111.0 IntroductionThis document is the datasheet for the Intel® 82854 Graphics Memory Controller Hub (GMCH). 1.1 OverviewThe

Intel® 82854 Graphics Memory Controller Hub (GMCH)110 D15343-0034.11.21 PMCS – Power Management Control/Status Register (Device #2)Address Offset:De

Intel® 82854 GMCH System Address MapD15343-003 1115.0 Intel® 82854 GMCH System Address MapA system based on the GMCH supports 4 GB of addressable sy

Intel® 82854 Graphics Memory Controller Hub (GMCH)112 D15343-0035.2 DOS Compatibility AreaThis compatibility region is divided into the following ad

Intel® 82854 GMCH System Address MapD15343-003 113Table 26. System Memory Segments and Their AttributesDOS Area (000000h-09FFFFh)The DOS area is 64

Intel® 82854 Graphics Memory Controller Hub (GMCH)114 D15343-003Monochrome Display Adapter (MDA) Range (0B0000h - 0B7FFFh)Monochrome Display Adapter

Intel® 82854 GMCH System Address MapD15343-003 1155.4 Main System Memory Address Range (0010_0000h to Top of Main Memory)The address range from 1 MB

Intel® 82854 Graphics Memory Controller Hub (GMCH)116 D15343-0035.4.2.1 Extended SMRAM Address Range (HSEG and TSEG)The HSEG and TSEG SMM transactio

Intel® 82854 GMCH System Address MapD15343-003 1175.4.2.5 PCI Memory Address Range (Top of Main System Memory to 4 GB)The address range from the top

Intel® 82854 Graphics Memory Controller Hub (GMCH)118 D15343-0035.4.3 System Management Mode (SMM) Memory RangeThe GMCH supports the use of main sys

Intel® 82854 GMCH System Address MapD15343-003 119Table 28. SMM Space Transaction Handling5.4.4 System Memory ShadowingAny block of system memory t

Intel® 82854 Graphics Memory Controller Hub (GMCH)12 D15343-003System Interrupts• Supports Intel 8259 and front side bus interrupt delivery mechanis

Intel® 82854 Graphics Memory Controller Hub (GMCH)120 D15343-0035.4.5.1 PCI I/O Address MappingThe GMCH can be programmed to direct non-memory (I/O)

Intel® 82854 GMCH System Address MapD15343-003 1215.4.7 Hub Interface Decode Rules The GMCH accepts accesses from Hub interface to the following add

Intel® 82854 Graphics Memory Controller Hub (GMCH)122 D15343-0035.4.7.2 Interface Decode RulesCycles Initiated Using PCI ProtocolThe GMCH does not s

Functional DescriptionD15343-003 1236.0 Functional Description6.1 Host Interface Overview The GMCH front side bus uses source synchronous transfer f

Intel® 82854 Graphics Memory Controller Hub (GMCH)124 D15343-003MSI is dependent on the address of the interrupt Memory Write. The GMCH forwards inb

Functional DescriptionD15343-003 125series of I/O cycles to the south bridge. The BIOS needs to determine the size and type of system memory used f

Intel® 82854 Graphics Memory Controller Hub (GMCH)126 D15343-0036.4 Integrated Graphics OverviewThe Intel® 82854 GMCH provides a highly integrated g

Functional DescriptionD15343-003 1276.4.2 3D EngineThe 3D engine of the GMCH has been designed with a deeply pipelined architecture, where performan

Intel® 82854 Graphics Memory Controller Hub (GMCH)128 D15343-003The scissor rectangle accelerates the clipping process by allowing the driver to cli

Functional DescriptionD15343-003 1296.4.2.10 Texture ChromakeyChromakey is a method for removing a specific color or range of colors from a texture

IntroductionD15343-003 13Display• Analog display support— 350-MHz integrated 24-bit RAMDAC that can drive a standard progressive scan analog monitor

Intel® 82854 Graphics Memory Controller Hub (GMCH)130 D15343-003Maps. Trilinear MIP Mapping is used minimize the visibility of LOD transitions acro

Functional DescriptionD15343-003 1316.4.3.1 Texture Map BlendingMultiple textures can be blended together in an iterative process and applied to a p

Intel® 82854 Graphics Memory Controller Hub (GMCH)132 D15343-003The GMCH supports both types of fog operations, vertex and per pixel. If fog is disa

Functional DescriptionD15343-003 133reasonably accurate depth buffering within inches of the eye point. The selection of depth buffer size is relat

Intel® 82854 Graphics Memory Controller Hub (GMCH)134 D15343-003Data is horizontally and vertically aligned at the destination. If the destination

Functional DescriptionD15343-003 1356.4.6.1 Cursor Color FormatsColor data can be in an indexed format or a true color format. Indexed data uses th

Intel® 82854 Graphics Memory Controller Hub (GMCH)136 D15343-0036.4.7.5 Color ControlColor control provides a method of changing the color character

Functional DescriptionD15343-003 1376.4.8 Video FunctionalityThe GMCH supports MPEG-2 decoding hardware, sub-picture support and DTV. 6.4.8.1 MPEG-2

Intel® 82854 Graphics Memory Controller Hub (GMCH)138 D15343-0036.5 Internal Graphic Display InterfaceThe GMCH has three dedicated display ports: an

Functional DescriptionD15343-003 1396.5.1.1 ARIB SupportPlease refer to the ARIB TR-B15 Operational Guidelines for Digital Satellite Broadcasting (d

Intel® 82854 Graphics Memory Controller Hub (GMCH)14 D15343-003• 3D graphics engine — 3D setup and render engine— Enhanced Hardware Binning Instru

Intel® 82854 Graphics Memory Controller Hub (GMCH)140 D15343-0036.5.1.3 HSYNC/VSYNC Field TimingThe interlace timing is provided on the timing gener

Functional DescriptionD15343-003 141Following conditions should be met for the sync (HSYNC, VSYNC) and blank (HBLANK, VBLANK) signals: • Start of H

Intel® 82854 Graphics Memory Controller Hub (GMCH)142 D15343-0036.5.3.2 ARIB 960 X 540 support In order to support the conversion of a 960x540 or a

Functional DescriptionD15343-003 1436.5.4 Interlace support for Video Overlay WindowIn interlace mode, support for Field1 and Field2 timing generati

Intel® 82854 Graphics Memory Controller Hub (GMCH)144 D15343-003Figure 11 shows how the timing registers switch while the buffer 0 and buffer 1 are

Functional DescriptionD15343-003 1456.5.5 Analog Display Port CharacteristicsThe Analog display port provides an RGB signal output along with an HSY

Intel® 82854 Graphics Memory Controller Hub (GMCH)146 D15343-003

Power and Thermal ManagementD15343-003 1477.0 Power and Thermal ManagementThe Intel® 82854 GMCH is intended to be compliant with the following speci

Intel® 82854 Graphics Memory Controller Hub (GMCH)148 D15343-0037.1 General Description of Supported CPU StatesC0 (Full On): This is the only state

Power and Thermal ManagementD15343-003 1497.3 Internal Thermal SensorThis section describes the new on-die Thermal sensor capability. 7.3.1 Overview

IntroductionD15343-003 15— Dithering— Line and full-scene anti-aliasing— 16- and 24-bit Z buffering— 16- and 24-bit W buffering— 8-bit Stencil buffe

Intel® 82854 Graphics Memory Controller Hub (GMCH)150 D15343-0037.4 External Thermal Sensor InputAn External Thermal sensor with a serial interface

Intel® 82854 GMCH Strap PinsD15343-003 1518.0 Intel® 82854 GMCH Strap Pins8.1 Strapping Configuration Table 33. Strapping Signals and Configuration

Intel® 82854 Graphics Memory Controller Hub (GMCH)152 D15343-003Table 34. Intel® 82854 GMCH Straps for Frequency/CPU ConfigurationGST[2:0] LCLKCTLB

Ballout and Package InformationD15343-003 1539.0 Ballout and Package InformationFigure 12. Intel® 82854 GMCH Ballout Diagram (Top View)292827262524

Intel® 82854 Graphics Memory Controller Hub (GMCH)154 D15343-0039.1 VCC/VSS Voltage GroupsTable 35. Voltage Levels and Ball Out for Voltage GroupsN

Ballout and Package InformationD15343-003 155Table 36. Ballout Table Row Column Signal Name Row Column Signal Name Row Column Signal NameE 5 ADDID[

Intel® 82854 Graphics Memory Controller Hub (GMCH)156 D15343-003Row Column Signal Name Row Column Signal Name Row Column Signal NameY 25 HA[21]# F 2

Ballout and Package InformationD15343-003 157Row Column Signal Name Row Column Signal Name Row Column Signal NameK 27 HDSTBP[0]# H 10 HSYNC T 7 MDDC

Intel® 82854 Graphics Memory Controller Hub (GMCH)158 D15343-003Row Column Signal Name Row Column Signal Name Row Column Signal NameAD 28 RSTIN# AB

Ballout and Package InformationD15343-003 159Row Column Signal Name Row Column Signal Name Row Column Signal NameAG 22 SDQ[47] AG 2 SDQS[0] AC 21 SR

Intel® 82854 Graphics Memory Controller Hub (GMCH)16 D15343-003Package 732-pin Micro-FCBGA (37.5 x 37.5 mm)Figure 1. Intel® 854 Chipset system blo

Intel® 82854 Graphics Memory Controller Hub (GMCH)160 D15343-003Row Column Signal Name Row Column Signal Name Row Column Signal NameB 14 VCC1_5 AJ 6

Ballout and Package InformationD15343-003 161Row Column Signal Name Row Column Signal Name Row Column Signal NameAJ 26 VSS U 22 VSS AA 18 VSSAB 26 V

Intel® 82854 Graphics Memory Controller Hub (GMCH)162 D15343-003Row Column Signal Name Row Column Signal Name Row Column Signal NameAB 13 VSS L 9 VS

Ballout and Package InformationD15343-003 163Row Column Signal NameH22 VTTLFU21 VTTLFR21 VTTLFN21 VTTLFL21 VTTLFH20 VTTLFA20 VTTLFJ19 VTTLFH18 VTTLF

Intel® 82854 Graphics Memory Controller Hub (GMCH)164 D15343-0039.2 Package Mechanical InformationFigure 13 through Figure 15 provide detail on the

Ballout and Package InformationD15343-003 165Figure 14. Intel® 82854 GMCH Micro-FCBGA Package Dimensions (Side View)

Intel® 82854 Graphics Memory Controller Hub (GMCH)166 D15343-003Figure 15. Intel® 82854 GMCH Micro-FCBGA Package Dimensions (Bottom View)

IntroductionD15343-003 171.2 TerminologyTable 1. Terms and DescriptionsTerm DescriptionAGTL+ Advanced Gunning Transceiver Logic + (AGTL+) busBLI Ba

Intel® 82854 Graphics Memory Controller Hub (GMCH)18 D15343-003Intel 82801DBM ICH4-M The component contains the primary PCI interface, LPC interface

IntroductionD15343-003 191.3 Reference DocumentsTable 2. Reference DocumentsDocument LocationIntel® Celeron® M Processor Datasheet http://www.intel

2 D15343-003INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO

Intel® 82854 Graphics Memory Controller Hub (GMCH)20 D15343-003

Intel® 82854 GMCH OverviewD15343-003 212.0 Intel® 82854 GMCH Overview2.1 System ArchitectureThe Intel® 82854 GMCH includes a processor interface, DD

Intel® 82854 Graphics Memory Controller Hub (GMCH)22 D15343-0032.2 Processor Host InterfaceThe Intel® 82854 GMCH supports the Intel Celeron M Proces

Intel® 82854 GMCH OverviewD15343-003 23The GMCH system memory architecture is optimized to maintain open pages (up to 16-KB page size) across multip

Intel® 82854 Graphics Memory Controller Hub (GMCH)24 D15343-0032.6 Hub InterfaceA proprietary interconnect connects the GMCH to the ICH4-M. All comm

Intel® 82854 GMCH OverviewD15343-003 252.8 GMCH ClockingThe GMCH has the following clock input/output pins: • 400-MHz, spread spectrum, low voltage

Intel® 82854 Graphics Memory Controller Hub (GMCH)26 D15343-0032.9 System InterruptsThe GMCH supports both the legacy Intel 8259 Programmable Interr

Signal DescriptionD15343-003 273.0 Signal DescriptionThis section describes the Intel® 82854 GMCH signals. These signals are arranged in functional

Intel® 854 Graphics Memory Controller Hub (GMCH)28 D15343-0033.1 Host Interface SignalsTable 5. Host Interface Signal DescriptionsSignal Name Type

Signal DescriptionD15343-003 29DRDY# I/OAGTL+ Data Ready: Asserted for each cycle that data is transferred.HA[31:3]# I/O AGTL+ Host Address Bus: HA

D15343-003 3ContentsContents1.0 Introduction...

Intel® 854 Graphics Memory Controller Hub (GMCH)30 D15343-003RS[2:0]# O AGTL+Response Status: Indicates the type of response according to the follo

Signal DescriptionD15343-003 313.2 DDR SDRAM InterfaceTable 6. DDR SDRAM Interface Descriptions Signal Name Type DescriptionSCS[3:0]# O SSTL_2Chip

Intel® 854 Graphics Memory Controller Hub (GMCH)32 D15343-0033.3 Hub Interface SignalsTable 7. Hub Interface Signals SMAB[5,4,2,1] OSSTL_2Memory Ad

Signal DescriptionD15343-003 333.4 ClocksTable 8. Clock SignalsSignal Name Type DescriptionHost Processor ClockingBCLKBCLK#ICMOSDifferential Host C

Intel® 854 Graphics Memory Controller Hub (GMCH)34 D15343-003DPMS I DVODisplay Power Management Signaling: This signal is used only in mobile system

Signal DescriptionD15343-003 353.5 Internal Graphics Display SignalsThe IGD has support for DVOB/C interfaces, and an Analog CRT port.Digital Video

Intel® 854 Graphics Memory Controller Hub (GMCH)36 D15343-0033.5.2 Digital Video Output C (DVOC) PortTable 10. Digital Video Output C (DVOC) Port S

Signal DescriptionD15343-003 37Table 11. DVOB and DVOC Port Common Signal Descriptions 3.5.3 Analog CRT DisplayTable 12. Analog CRT Display Signal

Intel® 854 Graphics Memory Controller Hub (GMCH)38 D15343-0033.5.4 General Purpose Input/Output SignalsTable 13. GPIO Signal DescriptionsGPIO I/F T

Signal DescriptionD15343-003 393.6 Voltage References, PLL PowerTable 14. Voltage References, PLL Power Signal Name Type DescriptionHost ProcessorH

4 D15343-003Intel® 82854 Graphics Memory Controller Hub (GMCH) 4.8.4 PCI Status Register ...

Intel® 854 Graphics Memory Controller Hub (GMCH)40 D15343-003Hub InterfaceHLRCOMP Analog Hub Interface RCOMP: This signal is connected to a referenc

Register DescriptionD15343-003 414.0 Register Description4.1 Conceptual Overview of the Platform Configuration StructureThe GMCH and ICH4-M are phys

Intel® 82854 Graphics Memory Controller Hub (GMCH)42 D15343-0034.2 Nomenclature for Access AttributesTable 16 provides the nomenclature for the acce

Register DescriptionD15343-003 434.3 Standard PCI Bus Configuration MechanismThe PCI Bus defines a slot based “configuration space” that allows each

Intel® 82854 Graphics Memory Controller Hub (GMCH)44 D15343-0034.4.2 Primary PCI and Downstream Configuration MechanismIf the Bus Number in the CONF

Register DescriptionD15343-003 45system initialization software (usually BIOS) to properly determine the DDR SDRAM configurations, operating paramet

Intel® 82854 Graphics Memory Controller Hub (GMCH)46 D15343-003Bit Descriptions31 Configuration Enable (CFGE): When this bit is set to 1, accesses

Register DescriptionD15343-003 474.6.2 CONFIG_DATA – Configuration Data RegisterCONFIG_DATA is a 32-bit Read/Write window into Configuration Space.

Intel® 82854 Graphics Memory Controller Hub (GMCH)48 D15343-0034.7 VGA I/O Mapped RegistersIf Native Graphics mode is strapped, and Device #2 is ena

Register DescriptionD15343-003 494.8 Intel 854 GMCH Host-Hub Interface Bridge Device Registers (Device #0, Function #0)Table 5 summarizes the config

D15343-003 5Contents4.10.9 SVID – Subsystem Vendor Identification Register...974.10.10 ID – Subsystem Id

Intel® 82854 Graphics Memory Controller Hub (GMCH)50 D15343-003Aperture Translation Table BaseATTBASE B8 BB 00000000h RO, R/WHost Error Control/Stat

Register DescriptionD15343-003 514.8.1 VID – Vendor Identification RegisterThe VID Register contains the vendor identification number. This 16-bit r

Intel® 82854 Graphics Memory Controller Hub (GMCH)52 D15343-0034.8.3 PCICMD – PCI Command RegisterSince GMCH Device #0 does not physically reside on

Register DescriptionD15343-003 534.8.4 PCI Status RegisterPCISTS is a 16-bit status register that reports the occurrence of error events on Device #

Intel® 82854 Graphics Memory Controller Hub (GMCH)54 D15343-0034.8.5 RID – Register IdentificationThis register contains the revision number of the

Register DescriptionD15343-003 554.8.7 BCC – Base Class Code Register This register contains the Base Class code of the GMCH Device #0. This code is

Intel® 82854 Graphics Memory Controller Hub (GMCH)56 D15343-0034.8.10 SID – Subsystem Identification Register This value is used to identify a parti

Register DescriptionD15343-003 574.8.12 CAPID – Capabilities Identification Register (Device #0) The Capability Identification Register uniquely ide

Intel® 82854 Graphics Memory Controller Hub (GMCH)58 D15343-0034.8.13 GMC – GMCH Miscellaneous Control Register (Device #0) Address Offset:Default V

Register DescriptionD15343-003 594.8.14 GGC – GMCH Graphics Control Register (Device #0) Address Offset:Default Value:Access:Size:52-53h0030hRead/Wr

6 D15343-003Intel® 82854 Graphics Memory Controller Hub (GMCH) 6.4.1 3D/2D Instruction Processing ...

Intel® 82854 Graphics Memory Controller Hub (GMCH)60 D15343-0034.8.15 DAFC – Device and Function Control Register (Device #0) This 16-bit register c

Register DescriptionD15343-003 614.8.17 PAM(6:0) – Programmable Attribute Map Register (Device #0) The GMCH allows programmable DDR SDRAM attributes

Intel® 82854 Graphics Memory Controller Hub (GMCH)62 D15343-003As an example, consider a BIOS that is implemented on the Expansion bus. During the i

Register DescriptionD15343-003 63Table 21. PAM Registers and Associated System Memory SegmentsFor details on overall system address mapping scheme

Intel® 82854 Graphics Memory Controller Hub (GMCH)64 D15343-003Extended System BIOS Area (E0000h-EFFFFh)This 64-kB area is divided into four 16-kB s

Register DescriptionD15343-003 654.8.19 ESMRAMC – Extended System Management RAM Control (Device #0) The Extended SMRAM register controls the config

Intel® 82854 Graphics Memory Controller Hub (GMCH)66 D15343-0034.8.20 ERRSTS – Error Status Register (Device #0) This register is used to report var

Register DescriptionD15343-003 674.8.21 ERRCMD – Error Command Register (Device #0) This register enables various errors to generate a SERR Hub Inte

Intel® 82854 Graphics Memory Controller Hub (GMCH)68 D15343-0034.8.22 SMICMD – SMI Error Command Register (Device #0) This register enables various

Register DescriptionD15343-003 694.8.23 SCICMD – SCI Error Command Register (Device #0) This register enables various errors to generate a SCI Hub I

D15343-003 7ContentsFigures1 Intel® 854 Chipset system block diagram (Native Graphic mode) ...162 Configurat

Intel® 82854 Graphics Memory Controller Hub (GMCH)70 D15343-0034.8.24 SHIC – Secondary Host Interface Control Register (Device #0) Address Offset:De

Register DescriptionD15343-003 714.8.25 HEM – Host Error Control, Status, and Observation (Device #0) Address Offset:Default Value:Access:Size:F0-F3

Intel® 82854 Graphics Memory Controller Hub (GMCH)72 D15343-0034.9 Intel 854 GMCH Main Memory Control, Memory I/O Control Registers (Device #0, Func

Register DescriptionD15343-003 734.9.1 VID – Vendor Identification RegisterThe VID Register contains the vendor identification number. This 16-bit r

Intel® 82854 Graphics Memory Controller Hub (GMCH)74 D15343-0034.9.3 PCICMD – PCI Command RegisterSince Intel chipset Device #0 does not physically

Register DescriptionD15343-003 754.9.4 PCISTS – PCI Status RegisterPCISTS is a 16-bit status register that reports the occurrence of error events on

Intel® 82854 Graphics Memory Controller Hub (GMCH)76 D15343-0034.9.5 RID – Revision Identification RegisterThis register contains the revision numbe

Register DescriptionD15343-003 774.9.8 HDR – Header Type RegisterThis register identifies the header layout of the configuration space. No physical

Intel® 82854 Graphics Memory Controller Hub (GMCH)78 D15343-0034.9.11 CAPPTR – Capabilities Pointer RegisterThe CAPPTR provides the offset that is t

Register DescriptionD15343-003 794.9.13 DRA – DRAM Row Attribute Register (Device #0)The DDR SDRAM Row Attribute Register defines the page sizes to

8 D15343-003Intel® 82854 Graphics Memory Controller Hub (GMCH) 29 Relation of DBI Bits to Data Bits ...

Intel® 82854 Graphics Memory Controller Hub (GMCH)80 D15343-0034.9.14 DRT – DRAM Timing Register (Device #0)This register controls the timing of the

Register DescriptionD15343-003 8127:26 Back To Back Read-Write commands spacing (DDR, same or different Rows/Bank): This field determines the RD-WR

Intel® 82854 Graphics Memory Controller Hub (GMCH)82 D15343-003 11 Activate to Precharge delay (tRAS), MAX:This bit controls the maximum number of

Register DescriptionD15343-003 834.9.15 PWRMG – DRAM Controller Power Management Control Register (Device #0)Address Offset:Default Value:Access:Siz

Intel® 82854 Graphics Memory Controller Hub (GMCH)84 D15343-00310 Reserved.9:1 Reserved0 Power State S1/S3 Refresh Control:0 = Normal Operation, Pen

Register DescriptionD15343-003 854.9.16 DRC – DRAM Controller Mode Register (Device #0)Address Offset:Default Value:Access:Size:70-73h00000081hRO, R

Intel® 82854 Graphics Memory Controller Hub (GMCH)86 D15343-0039:7 Refresh Mode Select (RMS): This field determines whether Refresh is enabled and,

Register DescriptionD15343-003 876:4 Mode Select (SMS). These bits select the special operational mode of the DDR SDRAM Interface. The special mod

Intel® 82854 Graphics Memory Controller Hub (GMCH)88 D15343-0034.9.17 DTC – DRAM Throttling Control Register (Device #0)Throttling is independent fo

Register DescriptionD15343-003 89Bit Description31:28 DDR SDRAM Throttle Mode (TMODE):Four bits control which mechanisms for Throttling are enabled

D15343-003 9ContentsRevision History§ §Date Revision DescriptionMarch 2005 1.0 Initial release of this document.June 2005 2.0Add support for Genuine I

Intel® 82854 Graphics Memory Controller Hub (GMCH)90 D15343-00327:24 Read Counter Based Power Throttle Control (RCTC): These bits select the Counte

Register DescriptionD15343-003 9115:12 Write Thermal Based Power Throttle Control (WTTC): These bits select the Thermal based Power Throttle Bandwid

Intel® 82854 Graphics Memory Controller Hub (GMCH)92 D15343-0034.10 Intel 854 GMCH Configuration Process Registers (Device #0, Function #3)See “Nome

Register DescriptionD15343-003 934.10.2 DID – Device Identification RegisterThis 16-bit register combined with the Vendor Identification register un

Intel® 82854 Graphics Memory Controller Hub (GMCH)94 D15343-0034.10.3 PCICMD – PCI Command RegisterSince the Intel® 82854 GMCH Device #0 does not ph

Register DescriptionD15343-003 954.10.4 PCISTS – PCI Status RegisterPCISTS is a 16-bit status register that reports the occurrence of error events o

Intel® 82854 Graphics Memory Controller Hub (GMCH)96 D15343-0034.10.5 RID – Revision Identification RegisterThis register contains the revision numb

Register DescriptionD15343-003 974.10.8 HDR – Header Type RegisterThis register identifies the header layout of the configuration space. No physical

Intel® 82854 Graphics Memory Controller Hub (GMCH)98 D15343-0034.10.11 CAPPTR – Capabilities Pointer RegisterThe CAPPTR provides the offset that is

Register DescriptionD15343-003 99Table 24. Intel® 82854 GMCH Configurations and Some Resolution Examples: Native Graphics ModeStraps Read Through