Intel IXP46X Manual do Utilizador descarregar pdf (Página 65)

Intel

IXP45X and Intel

IXP46X Product Line of Network Processors

February 2007 HDD

Document Number: 305261; Revision: 004 65

General Layout and Routing Guide—Intel

IXP45X and Intel

IXP46X Product Line of Network

Processors

Figure 23 and Figure 24 show good and poor design practices for via placement on

surface-mount boards.

Figure 25 shows minimum pad-to-pad clearance for surface-mount passive

components and PGA or BGA components.

Figure 23. Good Design Practice for VIA Hole Placement

B2266-01

25 mils min

Figure 24. Poor Design Practice for VIA Placement

B2267-01

Flush Via min

Potential Bridge min

1 2 ... 60 61 62 63 64 65 66 67 68 69 70 ... 107 108

IXP45X and Intel 1
HDD February 2007 2
Contents 3
Revision History 7
1.0 Introduction 9
1.2 Related Documentation 10
Acronyms and Abbreviations 11
B3777 -007 13
1.5 Typical Applications 14
2.0 System Architecture 15
Line of Network 16
Processors 16
IXP46X Product 16
3.1 Soft Fusible Features 17
3.2 DDR-266 SDRAM Interface 18
3.3 Expansion Bus 20
3.3.1 Signal Interface 21
IXP45X and 22
3.3.3 8-Bit Device Interface 23
3.3.4 16-Bit Device Interface 23
3.3.5 32-Bit Device Interface 24
8-Bit Device 25
16-Bit Device 25
32-Bit Device 25
3.4.1 Signal Interface 29
3.5 MII/SMII Interface 30
3.5.1 Signal Interface MII 31
VCC (3.3 V) 33
3.5.3 Signal Interface, SMII 34
3.6 GPIO Interface 35
3.6.1 Signal Interface 36
3.6.2 Design Notes 36
C Interface 37
B4104-002 38
3.8.1 Signal Interface 39
Host Device 40
Device Host 41
3.9.1 Signal Interface 42
3.9.2 Device Connection 42
B4107 -003 43
3.10.1 Signal Interface 44
B4109-001 47
3.12 PCI Interface 48
B4110- 001 50
Product Line 51
Network Processor 51
3.13 JTAG Interface 53
3.14 Input System Clock 54
3.15 Power 55
4.0 General PCB Guide 59
4.5 Stack-Up Selection 60
B2275-02 62
5.1 Overview 63
5.2 General Layout Guidelines 63
Return Current 64
25 mils min 65
B2268-01 66
5.2.5 USB Considerations 67
5.2.6 Cross-Talk 68
5.2.8 Trace Impedance 69
5.2.9 Power and Ground Plane 69
6.1 Electrical Interface 71
6.2 Topology 71
Network 73
Processor 73
6.3.2 Routing Guidelines 74
6.3.3 Signal Loading 74
7.0 DDR-SDRAM 75
B3986-001 76
IXP46X DDR SDRAM 80
Signal-Timing Analysis 81
B3989-001 82
B3990-001 83
7.1.5 Timing Relationships 87
7.1.7 Routing Guidelines 88
7.2 Simulation Results 90
7.2.2 Data Group 92
7.2.3 Control Group 98
7.2.4 Command Group 100
7.2.5 RCVENIN and RCVENOUT 105

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