manuais Intel IXF1104

Intel IXF1104 Manual do Utilizador (231 páginas)

Marca: Intel | Categoria: Placas-mãe | Tamanho: 3.18 MB |

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Media Access Controller

1

2 Datasheet

2

Document Number: 278757

10

Revision Number: 009

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Revision Date: 27-Oct-2005

10

Revision History

12

Contents

13

Datasheet 13

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14 Datasheet

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Datasheet 15

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16 Datasheet

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Datasheet 17

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18 Datasheet

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Datasheet 19

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1.0 Introduction

20

2.0 General Description

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Datasheet 22

22

3.1 Ball Assignments

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3.2 Ball List Tables

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Datasheet 25

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26 Datasheet

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Datasheet 27

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28 Datasheet

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Datasheet 29

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30 Datasheet

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Datasheet 31

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32 Datasheet

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Datasheet 33

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34 Datasheet

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Datasheet 35

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36 Datasheet

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4.1 Naming Conventions

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4.2 Interface Signal Groups

38

4.3 Signal Description Tables

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Datasheet 40

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41 Datasheet

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Datasheet 42

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43 Datasheet

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Datasheet 44

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45 Datasheet

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Datasheet 46

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47 Datasheet

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Datasheet 48

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49 Datasheet

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Datasheet 50

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51 Datasheet

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Datasheet 52

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53 Datasheet

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Datasheet 54

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Datasheet 56

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4.4 Ball Usage Summary

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Datasheet 60

60

4.6 Ball State During Reset

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Datasheet 62

62

4.7 Power Supply Sequencing

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4.9 Analog Power Filtering

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65 Datasheet

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Table 21. Analog Power Balls

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5.0 Functional Descriptions

66

5.1.1.3.4 Filter VLAN Packets

68

5.1.1.4 CRC Error Detection

69

5.1.2.1.1 Pause Frame Format

71

• OpCode of 00-01

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• Length/Type field of 88-08

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B3234-01

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5.1.3.1 Configuration

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• Per-Port Registers

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• Global Registers

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5.1.4 Fiber Mode

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5.1.4.3 Fiber Forced Mode

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5.1.5.1 Speed

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5.1.5.2 Duplex

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5.1.6.1 Rx Statistics

79

5.1.6.2 TX Statistics

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5.1.7.1.1 TX FIFO

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5.1.7.1.2 RX FIFO

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81 Datasheet

81

5.1.8.1 Conventions

82

5.2 SPI3 Interface

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Data Path

84

5.2.2.1 Transmit Timing

85

5.2.2.2 Receive Timing

85

B0660-02

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5.2.2.3 Clock Rates

87

5.2.2.4 Parity

87

5.2.2.5 SPHY Mode

87

5.2.2.5.1 Data Path

87

• TMOD[1:0]

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• RMOD[1:0]

88

89 Datasheet

89

5.2.2.8.1 Clock Rates

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5.2.2.8.2 Parity

91

5.2.2.9 SPI3 Flow Control

91

5.2.3 Pre-Pending Function

93

IXF1104

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Quad PHY Device

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95 Datasheet

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5.4.2 Timing Specifics

97

5.4.3 TX_ER and RX_ER Coding

97

Valid Frame

98

Frame with Error

98

5.4.3.1 In-Band Status

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• RXDV = true

99

5.5.1 MDIO Address

100

5.5.3 Clear When Done

100

5.5.4 MDC Generation

100

5.5.5 Management Frames

101

5.5.7 MDI State Machine

101

Datasheet 102

102

Figure 22. MDI State

102

• Data frequency of 1.25 GHz

103

.5 x 10 mA = 5 mA

104

5.6.2.4 Selective Power-Down

105

Frequency

106

Sinusoidal Jitter Mask

106

Peak-to-Peak Amplitude (UI)

106

• High-Speed Serial Interface

107

5.7.2 Functional Descriptions

108

5.7.3.1 I

110

C Control and Data Registers

110

5.7.3.2 I

110

C Read Operation

110

5.7.3.3 I

111

C Write Operation

111

5.7.3.6.1 Start Condition

113

5.7.3.6.2 Stop Condition

113

5.7.3.6.3 Acknowledge

114

5.7.3.6.4 Memory Reset

114

5.7.3.6.5 Device Addressing

114

5.8 LED Interface

115

1 22 23 24 25 26 27 28 29 30

116

13534333231302928272625234

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LED_DATA

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LED_LATCH

116

5.8.6.1.1 Fiber LED Behavior

119

5.9 CPU Interface

120

5.9.1 Functional Description

121

5.9.1.3 CPU Timing Parameters

122

5.10 TAP Interface (JTAG)

123

5.11 Loopback Modes

125

SPI3 Internal Loopback

126

5.12 Clocks

127

5.12.3 RGMII Clocks

128

5.12.4 MDC Clock

128

5.12.5 JTAG Clock

129

5.12.6 I

129

5.12.7 LED Clock

129

6.0 Applications

130

6.2.1 Disable Port Sequence

131

6.2.2 Enable Port Sequence

131

• 2.5 V CMOS

133

• 3.3 V LVTTL

133

• SerDes

133

Ω; 20% to

134

Datasheet 136

136

Table 45. RGMII Power

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137 Datasheet

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Datasheet 138

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139 Datasheet

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Datasheet 140

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(at Transmitter)

141

(at Receiver)

141

B0634-01

142

143 Datasheet

143

Datasheet 144

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7.6.3 MDIO AC Timing

146

7.7 Optical Module and I

147

C AC Timing Specification

147

Datasheet 148

148

Table 53. I

148

Datasheet 150

150

TxPauseAdd[1:0]

151

TxPauseFr

151

8.0 Register Set

155

8.3 Per Port Registers

156

8.4 Register Map

156

157 Datasheet

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Datasheet 158

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Datasheet 160

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8.4.1 MAC Control Registers

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Datasheet 166

166

167 Datasheet

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Datasheet 168

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Datasheet 170

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171 Datasheet

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Datasheet 172

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173 Datasheet

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Name Description Address Type

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Default

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175 Datasheet

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Datasheet 176

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177 Datasheet

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179 Datasheet

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Datasheet 180

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8.4.4 PHY Autoscan Registers

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Datasheet 182

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183 Datasheet

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Datasheet 184

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185 Datasheet

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Datasheet 186

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187 Datasheet

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189 Datasheet

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191 Datasheet

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Datasheet 192

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Table 112. JTAG ID ($0x50C)

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Datasheet 196

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197 Datasheet

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Bit Name Description Type

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Register Description:

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Datasheet 200

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201 Datasheet

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Datasheet 202

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Datasheet 204

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205 Datasheet

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Datasheet 206

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Datasheet 208

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209 Datasheet

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Datasheet 210

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8.4.8 MDIO Register Overview

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Datasheet 212

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8.4.9 SPI3 Register Overview

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Datasheet 214

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215 Datasheet

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Datasheet 216

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217 Datasheet

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Datasheet 218

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219 Datasheet

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221 Datasheet

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9.0 Mechanical Specifications

224

9.3 Package Information

225

B0555-01

226

Seating Plane

226

TOP VIEW

227

BOTTOM VIEW

227

Datasheet 228

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Datasheet 230

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231 Datasheet

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