Intel 8XC196Lx Manual do Utilizador descarregar pdf (Página 86)

8XC196L

SUPPLEMENT

8-20

J_DLY

Address:

Reset State:

1F58H

00H

The J1850 delay (J_DLY) register allows you compensate for the inherent propagation delays and to

accurately resolve bus contention during arbitration. This byte register can be directly addressed

through

windowing

7 0

— — — DLY4 DLY3 DLY2 DLY1 DLY0

Bit

Number

Bit

Mnemonic

Function

7:5 — Reserved; for compatibility with future devices, write zeros to these bits.

4:0 DLY4:0 Delay Time

These five bits specify the desired propagation delay between the J1850

controller circuitry and the off-chip transceiver device, in units of

microseconds (µs).

Figure 8-18. J1850 Delay (J_DLY) Register

1 2 ... 81 82 83 84 85 86 87 88 89 90 91 ... 135 136

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