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manuais Intel 80C188XL

Manuais de instruções e guias do utilizador para Hardware Intel 80C188XL.
Disponibilizamos 1 manuais Intel 80C188XL em pdf para descarga gratuita: Manual do Utilizador


Intel 80C188XL Manual do Utilizador (405 páginas)


Marca: Intel | Categoria: Hardware | Tamanho: 1.92 MB |

 

Índice

80C186XL/80C188XL

1

Microprocessor

1

User’s Manual

1

80C186XL/80C188XL

2

Microprocessor

2

© INTEL CORPORATION, 1995

3

CONTENTS

4

EXAMPLES

17

Introduction

18

CHAPTER 1

20

INTRODUCTION

20

1.3.2.1 How to Find

25

Overview of the

28

80C186 Family

28

Architecture

28

CHAPTER 2

30

OVERVIEW OF THE 80C186 FAMILY

30

ARCHITECTURE

30

A1012-0A

31

A1500-0A

32

A1033-0A

33

CS Code Segment

35

DS Data Segment

35

SS Stack Segment

35

ES Extra Segment

35

A1035-0A

38

A1036-0A

39

A1037-0A

40

A1038-0A

41

Free Space

43

A1013-0A

45

• Unsigned binary

48

• Signed binary (integers)

48

• Unsigned packed decimal

48

• Unsigned unpacked decimal

48

2.2.1.4 String Instructions

51

) for source string

52

) for destination string

52

A1015-0A

58

Opcode Mod R/M

59

Displacement

59

A1017-0A

60

A1018-0A

60

A1019-0A

61

A1020-0A

62

A1021-0A

62

A1022-0A

63

A1024-0A

64

Source EA

65

Destination EA

65

component; a 32-bit

66

Floating Point

66

Magnitude

67

A1028-0A

68

A1009-02

69

A1029-0A

71

2.3.1.2 Maskable Interrupts

72

2.3.1.3 Exceptions

72

A1030-0A

75

A1031-0A

76

A1032-0A

77

A1034-0A

78

Bus Interface Unit

80

CHAPTER 3

82

• Address/Status Phase

89

• Data Phase

89

Table 3-1. Bus Cycle Types

93

BUS INTERFACE UNIT

100

3.5.1.1 Refresh Bus Cycles

103

• An interrupt is generated

109

• A bus HOLD is generated

109

• A DMA request is generated

109

Figure 3-25. HALT Bus Cycle

110

NOTES: 

112

3.5.6 Exiting HALT

113

Figure 3-29. Exiting HALT

114

• Additional V

115

A1095-0A

116

A1058-0B

117

QS0, QS1

120

3.7.1.1 HOLD Bus Latency

121

Figure 3-36. Latching HLDA

124

Figure 3-37. Exiting HOLD

125

Peripheral Control

128

CHAPTER 4

130

PERIPHERAL CONTROL BLOCK

130

Register Mnemonic: RELREG

131

Function

132

Clock Generation and

138

Power Management

138

CHAPTER 5

140

CLOCK GENERATION AND POWER

140

MANAGEMENT

140

90˚ 180˚90˚

141

Z = Inverter Output Z

141

A1520-0A

142

5.1.1.2 Selecting Crystals

144

A1521-0A

146

A1508-0B

147

in the logic high state. If

148

A1523-0A

149

Register Mnemonic: PWRSAV

151

T2 T3 T4

152

Chip-Select Unit

154

CHAPTER 6

156

CHIP-SELECT UNIT

156

A1168-0A

157

Address Valid

159

Register Mnemonic: UMCS

162

chip-select

162

Register Mnemonic: LMCS

163

Register Mnemonic: MMCS

164

chip-selects

164

Register Mnemonic: PACS

165

Register Mnemonic: MPCS

166

and PCS chip

166

6.4.2.1 UCS Active Range

167

6.4.2.2 LCS Active Range

168

6.4.2.3 MCS Active Range

168

Table 6-4. MCS Active Range

168

A1136-0C

169

6.4.2.4 PCS Active Range

170

Table 6-6. PCS Active Range

170

Device select

173

External Master Chip Select

173

CSU Chip Select

173

Figure 6-13. Typical System

174

Refresh Control Unit

178

A1539-01

180

REFRESH CONTROL UNIT

181

A1502-0A

183

RFTIME equ xxxxh

190

Interrupt Control

194

CHAPTER 8

196

INTERRUPT CONTROL UNIT

196

8.2.1.1 Interrupt Masking

198

8.2.1.2 Interrupt Priority

198

8.2.1.3 Interrupt Nesting

199

INT3 Control 3EH

206

Figure 8-11. Poll Register

215

Interrupt

220

8.5.1.3 Other Registers

223

A1200-A0

225

Timer/Counter Unit

228

CHAPTER 9

230

TIMER/COUNTER UNIT

230

Register Mnemonic: T2CON

238

A1299-0A

239

A1300-0A

240

9.2.3.1 Retriggering

242

T1CMPB equ xxxxH

250

T1CMPA equ xxxxH

251

Direct Memory

254

Access Unit

254

CHAPTER 10

256

DIRECT MEMORY ACCESS UNIT

256

• from I/O space to I/O space

258

10.1.10.1.1 Fixed Priority

263

A1540-01

264

• pointer address

265

Register Mnemonic: DxDSTH

268

Destination pointer

268

Register Mnemonic: DxCON

270

Math Coprocessing

284

CHAPTER 11

286

MATH COPROCESSING

286

A1257-0A

293

A1531-0A

299

ONCE Mode

302

CHAPTER 12

304

ONCE MODE

304

A1532-0A

305

80C186 Instruction

306

Set Additions and

306

Extensions

306

APPENDIX A

308

80C186 INSTRUCTION SET

308

ADDITIONS AND EXTENSIONS

308

Figure A-4)

311

A1003-0A

312

A1004-0A

313

A1005-0A

314

• Data transfer instructions

315

• Arithmetic instructions

315

A.2.3.1 Shift Instructions

316

A.2.3.2 Rotate Instructions

317

Synchronization

318

APPENDIX B

320

INPUT SYNCHRONIZATION

320

Instruction Set

322

Descriptions

322

APPENDIX C

324

INSTRUCTION SET DESCRIPTIONS

324

Table C-4. Instruction Set

327

Opcodes and Clock

372

APPENDIX D

374

INSTRUCTION SET OPCODES

374

AND CLOCK CYCLES

374

Hex Binary

382

Byte 2 Immed Shift Grp1 Grp2

395

2-10, 2-13

402




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