Intel SE8500HW4 Manual do Utilizador Página 72
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Electrical Specifications Intel® Server Board Set SE8500HW4
Revision 1.0
Intel order number D22893-001
60
Table 35. Typical Power-Down Timings
Ref Description Max Typical Min
t1 Time from front-panel power button push, to BMC asserting the power button to the
chi
p
set. BMC debounces the
p
ower button in
p
ut for 50ms
1s 90ms 50ms
t2 Time from BMC asserting power button to chipset, until chipset responds with
SLP
_
S5
_
L. De
p
endent on chi
p
set setu
p
.
5s 4.5s –
t3 Time from when SLP_S5_L is asserted, to when BMC deasserts PS_ON_L to
complete system power-off.
1s 160ms 50ms
t4 Time from BMC deasserting D2D enable, to when it deasserts PS_ON_L to
complete system power-off.
– 100µs 0µs
8.3 Reset
Figure 16 and Table 36 illustrate the reset routing in the Intel
®
Server Board Set SE8500HW4.
VID_PCI_RST_N
XDP1
XDP2
ICH5
NB
RESET BUTTON
FWH1
FWH2
SIO
PLD 1
PLD 3
PLD 1
Proc1
Proc2
Proc3
Proc4
PB1_RESET_N
PB0_RESET_N
IMI CONN 1
IMI CONN 2
IMI CONN 3
IMI CONN 4
IMI Hotplug
IMI_A_ISO_RST_N
IMI_B_ISO_RST_N
IMI_C_ISO_RST_N
IMI_D_ISO_RST_N
Power
Connector
PS1_PWROK
LEVEL
TRANSLATOR
OR
GATE
PB1_RESET
PB0_RESET
IMI_A_RST_N
IMI_D_RST_N
IMI_B_RST_N
IMI_C_RST_N
IMI<D:A>_RST_EN_N
NB_RESETI_N
ITP_DBR_RESET_N
FP_RST_BTN_N
LPC_FWH_LRESET_N
LPC_SIO_LRESET_N
SIO_VID_RST
Front Panel
Connector
Video
PCI_IDE_RST_N
PXH
IOP332
PXH_RESETI_N
IOP332_RESETI_N
NB_R_RESETI_N
PCI_RESET_N
ICH5_SYS_RST_N
ITP_CPU_RESET_N
BUFFER
PCI_RST_BUFF1_N
SIO_NIC_RST
PS2_PWROK
Network
PX2B_RST_N
NIC_RST_N
Figure 16. Reset Block Diagram
- Server Board Set 1
- SE8500HW4 1
- Revision History 2
- Disclaimers 2
- Table of Contents 3
- List of Figures 8
- List of Tables 9
- Revision 1.0 10
- Revision 1.0 11
- 1. Product Overview 13
- 1.1 Board Set Features 14
- 2. Processor and Chipset 17
- 2.1.1 Heat Sink 18
- 2.1.2 Installation Order 19
- 2.2 Intel 20
- E8500 Chipset 20
- 3. I/O Subsystems 23
- 3.1.2 PCI IDSEL Signal 24
- 3.1.4 Wake On LAN 25
- 3.1.5 PCI Hot Plug* Support 26
- 3.2 Ultra320 SCSI Subsystem 28
- 3.3.1 Intel 29
- RAID Activation Key (RAK) 29
- 3.3.2 DDR2 RAID DIMM 29
- 3.3.3 Intel 29
- RAID Smart Battery (RSB) 29
- 3.4 Gigabit Ethernet 30
- 3.5 Serial ATA (SATA) 30
- 3.6 Fibre Channel 30
- 3.7 Firmware Hubs 30
- 3.8 Video 31
- 3.9 USB 2.0 31
- 3.10 Serial 31
- 4. Intel 33
- 4.1 DDR2 DIMM Support 34
- 4.2 Installation Order 34
- 4.3 Memory Initialization 34
- 4.5 Memory Board Components 35
- Table 8. Memory Board LEDs 37
- 4.6 Memory Hot Plug 38
- 5. Server Management 39
- Figure 8. I 41
- C Block Diagram 41
- 5.1.4 Rolling BIOS 43
- Table 11. Fan States 44
- 5.2.1 Memory Throttling 45
- 5.2.2 Processor Throttling 45
- 5.3 ACPI Power Control 46
- 5.4.1 FRB3 47
- 5.5 Reset Control 48
- Local Host 49
- 5.6.4 Serial Over LAN (SOL) 51
- Events 52
- 5.7.2 Dial Page Alerting 53
- 5.7.3 Alert over LAN 53
- 5.7.4 Alert over Serial/PPP 54
- 6. Jumpers 55
- Table 16. Mainboard Jumpers 56
- 6.1.2 Intel 57
- Management Module 57
- SOCKET 1 59
- SOCKET 34 59
- SOCKET 35 59
- SOCKET 68 59
- 68 POSITION DEVICE CONNECTOR 59
- 7.2 100-pin Front Panel 60
- 7.3 COM2 Serial Port 61
- 7.4 USB 62
- 7.5 SATA 62
- 7.6 Power 63
- 7.7 Rear Panel Connectors 64
- Yellow LED 66
- Green LED 66
- 7.7.4 USB 67
- 7.8.1 5-pin ICMB Header 67
- 7.8.2 3-pin IPMB Header 67
- C POST Code Headers 68
- 8. Electrical Specifications 69
- 8.2 Power Timing 70
- 8.2.2 Power-Down Sequence 71
- 8.3 Reset 72
- 8.4 Interrupts 73
- 8.5 Clocks 74
- Table 37. PLD Functions 75
- Figure 18. PLD Connections 75
- 9.1.1 Mainboard 77
- 9.1.2 Memory Board 79
- 9.2 Thermal Specifications 80
- 10. System BIOS 81
- 10.1.1 Sparing 82
- 10.1.2 Maximum Compatibility 82
- 10.1.3 Maximum Performance 83
- 10.1.4 Memory Mirroring 83
- 10.1.5 Memory RAID 83
- 10.2 Rolling BIOS 85
- 10.3 Initialization 85
- 10.3.2 Memory 87
- 10.3.3 I/O Devices 89
- 10.4 Remote Management 90
- 10.4.2 Keystroke Mappings 91
- 10.4.3 Limitations 91
- 10.5.1 Channel Access Modes 92
- 10.5.3 Serial Over LAN 92
- 10.6 Wired For Management 93
- 10.7 System Management BIOS 93
- 10.8 Security 93
- 11. BIOS User Interface 95
- 11.4 Error Manager 97
- 11.6 BIOS Setup Utility 106
- 11.6.2 Keyboard Commands 107
- Table 62. Main Menu 108
- Table 73. Mass Storage Menu 115
- 12. Error Handling 123
- 12.1.2 CPU Diagnostic LEDs 125
- 12.2 Beeps 126
- 12.3 POST Messages 127
- Reference Documents 132
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